Transcript CARE_28May - Indico

The Calorimeter Recorder
CARE
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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Contents
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29 May 2009
STATUS
PCBs
Features of CARE
Technical details of CARE
Details under discussion
Acknowledgements
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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STATUS
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The project was started in December 2008.
The PCB design in Jan 2009 by EN/ICE.
All design documentation from ~1996 is available!
The 3 x PCB layouts finished on 13 May 2009.
The PCBs is being fabricated at CERN (ready mid June).
Most components are available except:
– 3 types of Precidip connectors, expected mid of June.
– 2 MICREL timing circuits, samples confirmed.
• The first two prototypes ready for mid July?
• Next steps SOFTWARE both the FPGA, the ELMB, test
programs for debug @ test to be started.
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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Motherboard PCB Layout
Very fine lines (3 mil)
FPGA
TTC
CLK
ELMB
LVDS
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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CARE PCB Layouts …
FPGA
4 x GbE
FPGA
FPGA
CAN bus
9-pol DSUB
FPGA
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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Features of CARE
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The analog LKr signals are digitized at 40 MHz.
The CARE consists of 4 indentical sectors = “896 virtual modules”!
Each sector has 2 DDR2 SODIMM sockets with maximum 2 x 4 GB.
This corresponds to ~8.3 s, but can be more with memory managment.
Raw data correspond to 960 MBytes/s per sector with 16 CPDAS
channels.
Readout is done with 1 GbE links/sector = ~80 MBytes/s if jumbo frames.
The same mechanics as CPD to keep the 7000 CPDAS and CPDTR
cards.
80 MHz Clock as CPD with SoB and EoB (Start of Burst) and (End of
Burst).
CAN bus for the DCS (Slow Control).
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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Technical Details of CARE
• The data from CPDAS is transmitted via a LVDS-link @1.04
Gbits/s to the main FPGA (Lattice ECP2-50).
• The FPGA has 8 input double buffers (one per link), while one
buffer is written the data of the other is read out and put into a
DDR2 memory.
• The DDR2 works in a time interleaved mode with fixed time slots
for WR, RD and REFRESH operations.
• TTC input with one TTCRx to be compatible with the TELL1.
• The intellegent DCS is integrated on the motherboard with one
ELMB.
– It is used for storing and loading of the CPDAS registers.
– Communication with the FPGAs and TTCRx.
– Voltage and Temperature monitoring > 36 parameters/CARE.
• Standard LHC type of DCS for racks and crates?
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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CARE Readout (1 sector)
SIMULATION EXAMPLE
DDR2 IP command burst operation
WRITE EXAMPLE
1792 bytes takes 1006 ns
@125 MHz (=1781 MB/s)
Sum of the 8 LVDS links
960 MB/s
Raw data stored in packets
74 ts of 16 ch = 1776 bytes
+16 bytes with extra info.
GbE JUMBO frames should be used!
1 Gbps
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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Points to (discuss) 1
• Pernicka 80 MHz clock with 1 usec stop during which an asychronous reset
is transmitted to each CARE.
• Note, the CARE module is dead for 10 ms after the reset of the 80 MHz
clock due to the PLLs in the LVDS links chips. (But not the GbE links to
read status).
• Clock error checking as in the CPD (number of clocks received).
• The same clock 125 MHz is used for the GbE and FPGA.
• TTC clock not used inside CARE because it is 40 MHz.
• TTC can be used for input L0 pulse, L0 trigger information (channel B) plus
start/end of burst (but not the reset of the 80 MHz clock)?
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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Points to discuss (2)
• GbE is used as data output. The output protocol to be defined.
• GbE can be used as input (64 Bytes @ 1 MHz) in the same way as
TTC.
• Direct connection between CARE and PC as with the SLM without
NETWORK SWITCH is becoming very interesting. Because one PC
server chassis has 12 x 1 GbE links.
• How long is the response time of the CARE?
• Flow control needed maybe but depends on DAQ architecure.
• Tests and Error finding
– Analog “calibration” system is the same as the CPD.
– Digital signals can be injected instead of ADC data in the CPDAS.
– The DDR2 memories write and readable.
29 May 2009
Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler
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Acknowledgements
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Sophie Baron PH/ESE.
DigiKEY, US component with large stock and distributor.
Pascale Gattolliat, Internal Sales, ARROW CE International GmbH.
Alex Hahn, Lattice/Munich, FPGA support.
Brian Martin, ATLAS, GETB project.
Douglas Tserkezoglou, retired CERN, test system documentation.
Pacal Vulliez, PCB layout.
Nicole Wauquier, CERN EN/ICE(Assembly).
29 May 2009
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