Transcript AshokS-IEEE-SSCET-Presentation

VLSI Design Lab
PHASE NOISE IN PHASE-LOCKED LOOP CIRCUITS
Ashok Srivastava
Department of Electrical and Computer Engineering
School of Electrical Engineering & Computer Science
Louisiana State University, Baton Rouge, LA
Email: [email protected]
URL: http://www.ece.lsu.edu/ashok/index.html
2012 Southeast Symposium on Contemporary Engineering Topics
The 3rd SSCET, 31 August 2012 New Orleans, Louisiana
VLSI Design Lab
Outline of Presentation

Introduction
• Phase-Locked Loop (PLL) building blocks
• Phase noise and jitter
• Goals and objectives

Experimental study of phase noise in CMOS PLL
• Circuit design
• Phase noise superposition

Switchable PLL design with phase noise and jitter tests
• Design
• Analysis
• Experimental results
VLSI Design Lab
Outline of Presentation

Low power phase-locked loop with LC voltage-controlled oscillator
• Design
• Layout and simulation
• Experiment Results

Conclusion

References
VLSI Design Lab
Introduction – PLL Building Blocks
Input
+
-
PFD/CP
Feedback
Loop
Filter
Divider

Phase/Frequency Detector (PFD)

Charge Pump (CP)

Loop Filter (LF)

Voltage-Controlled Oscillator (VCO)

Frequency Divider (FD)
Output
VCO
VLSI Design Lab
Introduction – PLL Building Blocks
PFD
The PFD built by two D-flip-flops
and one NAND gate
VLSI Design Lab
Introduction – PLL Building Blocks
PFD outputs with same frequency inputs
PFD outputs different frequency inputs
VLSI Design Lab
Introduction – PLL Building Blocks
Charge Pump & Loop Filter
R is to improve the stability.
VDD
CP
C2 is to prevent the voltage jumps
on the control voltage.
ICP
S1
Loop Filter
VCTRL
S2
C1
C2
ICP
Transfer function:
F ( s) 
1  s
sC1
  RC1 neglecting C2
R
Resulting in a first order loop filter
VLSI Design Lab
Introduction – PLL Building Blocks
REF leading–UP high–Charge C1–VCTRL increase
VLSI Design Lab
Introduction – PLL Building Blocks
•VCO Feedback leading–DN high–Discharge C1–VCTRL decrease
VLSI Design Lab
Introduction – PLL Building Blocks
Current Starved Single-ended Voltage Control Oscillator
fO 
ID
1

n(t r  t f ) n  C L  VDD
VLSI Design Lab
Introduction – Phase Noise and Jitter
Phase noise (frequency domain) - A signal’s short-term instabilities
are usually characterized in terms of the single sideband noise
spectral density. It is expressed in decibel below the carrier per hertz
(dBc/Hz) and is defined as
 P ( f  f ,1Hz ) 
Ltotal f   10 log  noise 0

P
carrier


Pnoise ( f 0  f ,1Hz ) is the sideband noise power at offset frequency,  f
from the carrier frequency f .0
VLSI Design Lab
Introduction – Phase Noise and Jitter
Oscillator power spectrum with phase noise
f
f0
f0
f
Phase noise - the ratio of the area of the
rectangle with 1-Hz bandwidth at offset
Δf to the total area, approximately the
difference in the height
VLSI Design Lab
Introduction – Phase Noise and Jitter
Jitter and phase noise are different ways to express the same phenomenon.
Phase noise is the uncertainty of the waveform in the frequency domain and
jitter is characterization in time domain of the PLL output.
Jitter is the deviation of a waveform transition from its ideal position.
(1) The cycle jitter:
Tcn  Tn  T
Tn is the time of the nth cycle of the output waveform, and T is the average
period.
(2) The cycle-to-cycle jitter:
(3) The accumulated jitter:
Tccn  Tn1  Tn
N
Tacc   (Tn  T )
n 1
3rd
VLSI Design Lab
Introduction – Phase Noise and Jitter
where N is the N th cycle of the waveform. This accumulated jitter is
characterized and increased by time interval, ΔT, which is the time
difference between the reference and the observed transitions during
the measurement.
The RMS (root mean-squared) jitter, which is the value of one standard
deviation of the normal distribution, is more useful because this value
changes not much as the number of samples increases.
VLSI Design Lab
Introduction – Goals and Objectives
Develop a comprehensive phase noise model of PLL
Compare the modeled phase noise results with the corresponding
experimentally measured results on a phase-locked loop chip
fabricated in 0.5 m n-well CMOS process.
Design a programmable PLL frequency synthesizer. The frequency
synthesizer is implemented by LC VCO and a low power dualmodulus prescaler.
VLSI Design Lab
PHASE NOISE STUDY IN CMOS PLL
VLSI Design Lab
Phase Noise in PLL
Noise sources in a second order PLL
F (s) 
(1  RC1s )
C1s  C2 s  RC 2C1s 2
npfdcp(s)
ninput(s)
P
nvco(s)
nlf(s)
F(s)
KV
 out(s)
s
1/N
nd(s)
Each of the noise sources is shaped by the loop transfer function from the
corresponding noise voltage source to the output phase. The PLL open
loop transfer function is G( s)  I CP  F ( s)  Kv / s . The PLL closed loop
transfer function is H ( s)  G( s)
1  G( s) / N
VLSI Design Lab
Phase Noise in PLL
VCO: The closed loop transfer function of the VCO phase noise can be
calculated using the noise transfer function from nvco (s) to  out (s) , which
is given by,
out (s)
1
1


nvco (s) 1  Gvco (s) H vco (s) 1  (2 Kv / s)  (1/ N ) K p F ( s)
The power spectral density of the output phase noise can be obtained
as follows,
S outVCO ( )  S inVCO ( )
 out ( j )
2
nvco ( j )
2
VLSI Design Lab
Phase Noise in PLL
Input Reference: Assuming a noisy input signal, the response of the
loop to the phase variations in the input can be evaluated using a
similar method. For the PLL under consideration, the input noise
transfer function is given by,
(2 Kv / s) K p F ( s)
out ( s)
Gin (s)


ninput (s) 1  Gin ( s) H in ( s) 1  (2 Kv / s)  (1/ N ) K p F ( s)
The closed loop phase noise power spectrum of input reference phase
noise is given by,
2
 out ( j )
S outINPUT ( )  S inINPUT ( )
2
ninput ( j )
VLSI Design Lab
Phase Noise in PLL
Divider: The additive noise is injected at the input of the PFD and share
the same transfer function as the noise at the input terminal. Similarly,
the noise transfer function for divider can be described as follows,
(2 Kv / s) K p F ( s)
out ( s)
Gd ( s)


nd (s) 1  Gd (s) H d (s) 1  (2 Kv / s)  (1/ N ) K p F ( s)
and,
S outD ( )  S inD ( )
 out ( j )
n d ( j )
2
2
VLSI Design Lab
Phase Noise in PLL
PFD: noise model for PFD can be expressed by the following
equations,
G pfdcp ( s )
I out ( s )
(2 K v / s )  F ( s )


n pfdcp ( s ) 1  G pfdcp ( s ) H pfdcp ( s) 1  (2 K v / s)  (1/ N ) K p F ( s)
and,
S outPFDCP ( )  S inPFDCP ( )
 out ( j )
2
n pfdcp ( j )
2
Loop filter: Noise model for the loop filter can also be described by the
following equations,
Vout ( s )
(2 K v / s )


nlf ( s ) 1  Glf ( s ) H lf ( s ) 1  (2 K v / s )  (1/ N ) K p F ( s )
Glf ( s )
S outLF ( )  S inLF ( )
 out ( j )
nlf ( j )
2
2
VLSI Design Lab
Phase Noise in PLL
Total PLL Phase Noise (Superposition)
•
Phase
noise
caused
by
components
are
evaluated
separately.
•
Total phase noise is the sum of
them.
•
There is a peak in the spectrum
at loop bandwidth frequency.
•
Phase noise at low offset is
dominated by input noise.
•
Phase noise at high offset is
dominated by VCO noise.
VLSI Design Lab
EXPERIMENTAL STUDY OF PHASE
NOISE IN CMOS PLL
VLSI Design Lab
PLL Experimental Study – Circuit Design
VDD=5V
CP
N 8
I CP  30A
R  41 .5k
C1  43.3 pF
C 2  100 fF
ICP
UP
 in
S1
Loop Filter
VCTRL
PFD
 feedback
DN
S2
C1
C2
ICP
R
VLSI Design Lab
PLL Experimental Study – Circuit Design
PFD circuit, layout and simulation result:
Buffers
VLSI Design Lab
PLL Experimental Study – Circuit Design
Charge Pump circuit, layout:
VLSI Design Lab
PLL Experimental Study – Circuit Design
1/8 Frequency Divider circuit and layout:
Transmission gate D-flip-flop
A very small and simple design
VLSI Design Lab
PLL Experimental Study – Circuit Design
The differential VCO circuit and layout with biasing:
VDD
M3
M4
2.1/1.2
2.1/1.2
Output_a
Output_b
M1
In_a
M2
9.6/1.2
VBias
9.6/1.2
In_b
80/2
In_a
+ - +
+ - +
+ - +
Output_a
+ - +
In_b
Output_b
VLSI Design Lab
PLL Experimental Study – Circuit Design
The PLL chip layout with differential VCO.
VLSI Design Lab
PLL Experimental Study – Circuit Design
RF test board with mounted PLL chip
SMA connecting cables which provide repeatable electrical performance with
low noise injection to the chip are used in this measurement.
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
140
The tuning range of differential VCO.
130
Oscillation Frequency (MHz)
120
110
100
90
80
70
60
50
40
0.5
1
1.5
2
2.5
3
Bias Voltage (V)
3.5
4
4.5
5
The gain of the VCO is 30 MHz/V measured at 80 MHz. The free running
frequency of the VCO is f  f 0  K V Vctrl .
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
The open loop VCO has two pins: bias voltage and VCO output. Bias voltage
pin is connected to a dc 1.9V and the output frequency is 80 MHz. The open
loop means that only the VCO is working in this case and it is outside the PLL.
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
Experimental results of input reference clock phase noise at 80 MHz PLL output
frequency. The experimentally measured phase noise is between -70 to -103
dBc/Hz from 10 kHz to 10 MHz offset frequency at 10 MHz center frequency.
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
The experimentally measured divider open loop SSB phase noise at 80 MHz PLL
output frequency.
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
The experimentally measured PFD/CP open loop SSB phase noise at 80 MHz PLL
output frequency.
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
The experimentally measured loop filter open loop SSB phase noise at 80 MHz
PLL output frequency.
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
The PLL output phase noise is obtained by the superposition of the noises spectra from VCO,
input reference, divider, PFD and loop filter. There is a peak observed in VCO closed loop phase
noise when the offset frequency is near the predicted loop bandwidth, 800 kHz. The phase noise
of PLL follows the closed loop VCO phase noise beyond the PLL bandwidth. At low offset
frequencies, noise is dominated by the input reference clock since the loop gain tries to make the
phase of VCO stable.
VLSI Design Lab
PLL Experimental Study – Phase Noise Superposition
PLL with Differential VCO Phase Noise Study
-30
Calculated PLL output
Expermental PLL output
-35
Phase Noise (dBc/Hz)
-40
-45
-50
-55
-60
-65
-70
4
10
5
6
10
10
7
10
Frequency (Hz)
The experimentally measured phase noise of the fabricated CMOS PLL circuit follows
the calculated frequency dependence phase noise behavior and is in good
agreement.
VLSI Design Lab
PLL Experimental Study – Summary
 PLL based on differential VCO structures is designed and
fabricated in 0.5 μm CMOS technology.
 Simulation and experimental results on VCO phase noise are
shown which are used for PLL phase noise prediction.
 Predicted and measurement results of PLL phase noise are
compared which verify the phase noise prediction method.
VLSI Design Lab
PHASE NOISE AND JITTER STUDY IN CMOS
SWITCHABLE PHASE-LOCKED LOOP (PLL)
VLSI Design Lab
Switchable PLL – Design
Building blocks of a switchable PLL architecture
Local
Oscillator
FD
High Frequecy PLL (640MHz-800MHz)
PFD
Loopfilter
H_VCO
input
output
Divider
MUX
Low Frequency PLL (320MHz-640MHz)
PFD
Loopfilter
L_VCO
Divider
The switch includes a local oscillator, frequency detector (FD) and a two input multiplexer (MUX). The FD
compares it with the input signal.
VLSI Design Lab
Switchable PLL – Analysis
Switchable PLL outputs at different frequencies
The output of the switchable PLL at different frequencies where 320 MHz waveform is
the low frequency PLL (L_PLL) output and 1.12 GHz waveform is the high frequency
PLL (H_PLL) output. (L_PLL starts to oscillate after 60ns and H_PLL starts to oscillate
after 5ns).
VLSI Design Lab
Switchable PLL – Analysis
Frequency detector output
The function of RC in the frequency detector is to
translate the PFD output pulses into dc voltages
Stabilizing time versus offset frequency
If the input frequency is less than the reference frequency, which
is output of the local oscillator defined as 80 MHz, the output is at
low level; while if the input frequency is higher than the reference
frequency, the output is at high level. But if the input frequency is
closer to the reference frequency it will take more time to get the
dc output.
VLSI Design Lab
Switchable PLL – Experimental Results
Cadence/Virtuoso layout and microphotograph of the fabricated switchable PLL chip
The switchable PLL described in the present
work was fabricated in 0.5 μm n-well CMOS
process.
VLSI Design Lab
Switchable PLL – Experimental Results
Phase noise performance of VCO at 1GHz
The experimental results which
from open loop VCO circuit on
chip are in good agreement with
modeled phase noises which
calculated.
are
the
the
are
PLL phase noise at 700MHz carrier frequency
PLL phase noise before stress is -61dBc/Hz
at 10 kHz offset frequency and is around 104dBc/Hz at 1 MHz offset frequency. The
PLL phase noise increases by about 1-2 dB
relative to carrier power per Hertz after four
hours of hot carriers stress.
.
VLSI Design Lab
Switchable PLL – Experimental Results
Experimental results of PLL jitter
The experimental results of device
degradation
on
RMS
jitter
performance under different PLL
output frequencies due to hot carrier
effects. A 40 ps increase is observed
after 4 hours of stress.
Photograph of PLL jitter
VLSI Design Lab
Switchable PLL – Summary
 A new design is proposed to expand PLL tuning range without
sacrificing its speed and jitter and phase noise performances.
 Cadence/Spectre has been used for post-layout simulations for
jitter, phase noise and switchable frequency range.
 The chip is experimentally tested for jitter, phase noise and
switchable frequency range.
VLSI Design Lab
LOW POWER PHASE-LOCKED LOOP
WITH LC VOLTAGE-CONTROLLED
OSCILLATOR
VLSI Design Lab
LC VCO PLL – Design
Building blocks of a LC VCO PLL architecture
M
XO
fout
PFD
Loopfilter
VCO
N
Main Counter
PFD
Prescaler
 ( P  1) /  P
B
fout
Mode Control
N = (P+1)A+P(B-A)
= PB + A
A
Swallow Counter
The programmable PLL includes a general PLL block and a dual modulus prescaler. The output frequency can
reach to 1.2GHz in this design. In the design, the main counter is an 11-bit counter and the divider ratio can
reach 2047 and the Swallow Counter is a 7-bit counter with divider ratio 127. Thus, the maximum divider ratio
N = PB + A = 131135 where P=64, B=2047 and A=127 for 64/65 prescaler or N = 262143 where P=128,
B=2047 and A=127 for 128/129 prescaler.
VLSI Design Lab
LC VCO PLL – Design
LC VCO architecture
VDD
4/4
4/4
L
L
5nH
5nH
VCTRL
C
50/50
C
VDD
5/1.5
5/1.5
10/1
5/1
LC VCO frequency range is 900MHz-1.2GHz.
VLSI Design Lab
LC VCO PLL – Design
LC VCO architecture
Crystal oscillator circuit
OSCIN
R=1.8k
OSCOUT
XOSC_INV
XOSC_INV
FOSC
VLSI Design Lab
LC VCO PLL – Design
The 3rd order low pass loop filter schematic.
R3=9.1 k
From Charge Pump
R2=4.2 k
C3=4.7 nF
C1=4.7 nF
C2=47 nF
The transfer function of the loop filter is
Z ( s) 
1  s  T2
s  Ctot  (1  s  T1 )  (1  s  T3 )
T2  R2  C2
Ctot  C1  C2  C3
R C C
T1  2 2 1
Ctot
T3  R3  C3
To VCO
VLSI Design Lab
LC VCO PLL – Layout and Simulation
Layout of the PLL frequency synthesizer.
LC_VCO
Counter
Loop Filter
PFD_CP
Prescaler
The programmable PLL is implemented in 0.5 μm double poly
triple metal CMOS technology.
VLSI Design Lab
LC VCO PLL – Layout and Simulation
1.2 GHz PLL differential output waveforms
The voltage swing of the PLL output is from 1.36V to 1.72V.
VLSI Design Lab
LC VCO PLL – Experiment Results
The spectrum measurement setup
Ref

PFD
Loopfilter
N
VCO
Power
Splitter
Spectrum
Analyzer
PLL output is connected to a power splitter to fulfill the impedance match.
VLSI Design Lab
LC VCO PLL – Experimental Results
Power spectrum density measurement
The carrier power is -29 dBm which is 0.001mW.
VLSI Design Lab
LC VCO PLL – Experimental Results
PLL output phase noise
The in-band phase noise is -66.67 dBc/Hz at 10kHz offset frequency and phase
noise reaches -120dBc/Hz at 1MHz offset frequency.
VLSI Design Lab
LC VCO PLL – Summary
 The low power design of a 3V 30mW PLL frequency synthesizer
designed in 0.5 μm CMOS process is presented.
 The divider has a main counter, a swallow counter and control
logic. The on-chip inductor and n-MOSFET varactors are used
in the LC VCO design.
VLSI Design Lab
Conclusion
•
A 3rd order PLL circuit is designed and an attempt has been made to model
phase noise based on superposition of phase noises from its following
circuit building blocks: the input reference, VCO, frequency divider, PFD
and the loop filter.
•
A new design is proposed to expand PLL tuning range without sacrificing its
speed and jitter and phase noise performances.
•
A low power design of a frequency synthesizer designed in 0.5 μm CMOS
process is presented.
VLSI Design Lab
References
1.
Y. Liu, A. Srivastava and Y. Xu, “Switchable PLL frequency synthesizer and hot carrier effects,” Journal of Circuits and
Systems, Vol. 2, No. 1, pp.45-52, Jan. 2011.
2.
Y. Liu, A. Srivastava and Y. Xu, “A switchable PLL frequency synthesizer and hot carrier effects,” Proc. ACM Great Lakes
Symposium on VLSI, pp. 481-486, May 10-12, 2009, (Boston, MA).
3.
Y. Liu and A. Srivastava, “Reliability considerations in switchable PLL frequency synthesizers for wireless sensor networks,”
Proc. SPIE Nano-, Bio-, Info-Tech Sensors and Systems, vol. 7646, pp. 7646-28, March 7-9, 2010, (San Diego, CA).
4.
Y. Liu and A. Srivastava, “Hot carrier effects on CMOS phase-locked loop frequency synthesizers,” Proc. International
Symposium on Quality Electronic Design (ISQED), pp. 92-98, March 22-24, 2010, (San Jose, CA).
5.
Y. Liu and A. Srivastava, “Effect of hot carrier injection and negative bias temperature instability on the performance of
CMOS phase-locked loops,” Proc. 2010 ASEE-GSW Annual conference, Mar. 24-26, 2010, (Lake Charles, LA).
6.
A. Srivastava, Y. Xu, Y. Liu, A. K. Sharma, and C. Mayberry, “CMOS LC voltage-controlled oscillator design using carbon
nanotube wire inductor,” Proc. 5th IASTED International Symposium on Circuits and Systems, pp. 171-176, August 23 – 25,
2010, (Maui, Hawaii).
7.
A. Srivastava, Y. Xu, Y. Liu, A. K. Sharma, and C. Mayberry, “CMOS LC voltage-controlled oscillator design using
multiwalled carbon nanotube wire inductor,” Proc. IEEE International Symposium on Electronic System Design (ISED),
December 20-22, 2010, (Bhubaneswar, India).
8.
A. Srivastava, Y. Xu, Y. Liu, A.K. Sharma, and C. Mayberry, ‘‘CMOS LC voltage controlled oscillator design using carbon
nanotube wire inductors,” ACM Journal on Emerging Technologies in Computing Systems, in Production (2012).
VLSI Design Lab
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