Transcript Performance and Calibration of the X

Development of CCDs and Relevant
Electronics for the X-ray CCD
camera of the MAXI Experiment
onboard the International Space
Station
Osaka University
E. Miyata, C. Natsukari, T. Kamazuka, H. Kouno, H. Tsunemi
NASDA (National Space Agency of Japan)
M. Matsuoka, H. Tomida, S. Ueno, K. Hamaguchi
Graduate University for Advanced Studies
I. Tanaka
OUTLINE
• International Space Station
• MAXI : Monitor of All-sky X-ray Image
• X-ray CCD Camera onboard MAXI --- SSC
• Engineering Models of SSC components
• Development of Electronics for SSC
• Summary
International Space Station (ISS)
International Space Station
is now constructing
mainly by USA, Russia, ESA, Japan, Canada
will be completed in 2006
go around the Earth in 90 min
©NASA/NASDA
MAXI : Monitor of All-Sky X-ray
Image
Radiator
for X-ray
CCDs
• mission
to monitor
the allGrapple Fixture for a robot arm sky in X-ray wave length
from ISS
• selected as an early payload
Electronics
of the JEM Exposed Facility
will be launched in 2005 by
Optical• Star
Sensor
100cm
HIIA rocket
• carry two sensors
– Gas Slit Camera (GSC)
poster 4497-18
– Solid-state Slit Camera
(SSC)
80cm
• mission life ~ 2yr
180cm
Gas Slit Cameras (GSC)
= X-ray gas counter cameras
Solid-state Slit
Cameras (SSC)
= X-ray CCD
cameras
Total weight: 500 kg
SSC
Solid-state Slit Camera
No of chip
16chips/SSC
Energy band
0.5-10 keV
Sensitivity
5.6mCrab/day
Effective area 100cm2/SSC
FOV
1x90
360x90 (1 orbit)
Pointing accuracy
Clocking
0.1x0.1
Parallel-summing
(Fast@ASCA)
R3081
Cooling System for SSC
• Two passive radiators
• Loop heat pipe is attached
– function as a heat switch
• Operating temperature of CCD:
– —100~ — 70 oC at BOL
– —85~ — 50 oC at EOL
(Peltier cooler is also used)
EM of AE for SSC
• There are several techniques to process the CCD video signal
• We have developed
– correlated double sampling
– delay circuit (used in ASCA/SIS)
– integration circuit (used in Chandra/ACIS, HETE2/SXC, Astro-E/XIS)
• We selected the integration circuit for the flight model
EM of SSC Camera
EM of CCD
•
•
•
•
•
fabricated by Hamamatsu Photonics K.K.
1024x1024 pixels of 24 µm
two phase gate structure
3-side buttable
single stage Peltier cooler
– same size as the CCD
– reduce the shock stress
• coated by 2000Å Al
• fabricated sample chips both from
– high-resistivity epitaxial wafer
– bulk wafer (+ n+ layer)
• To improve the radiation hardness
– using Si3N4 gate
– having notch structure
– having charge injection gate
Radiation Damage Test with
Proton
• We are now performing the radiation damage test using
the Van-de-Graaff accelerator in our faculty
• We will verify our improvements
and test the charge injection method to recover
100 keV
2MeV
4MeV
To Evaluate & Maximize
the CCD Performance
We need to optimize
clocking pattern and clocking voltages
(high energy resolution, high Q.E. etc.)
clocking pattern
to recover the performance for
a degraded chip due to radiation damage
(charge injection method etc.)
 We need highly flexible CCD driver system !
Previous Driver System
Use DAC to determine high & low levels for each clock
Use analog switch to select the voltage levels
high
DAC
D I/O
low
high
low
Analog
Switch
OP
amp
Analog
Switch
OP
amp
Analog
Switch
OP
amp
Analog
Switch
OP
amp
CCD
X Low flexibility
Δ Relatively complex circuit
O Small number of digital I/O pins
New Concept: Fast DAC & Fast
FPGA
Analog
DAC
Switch
FPGA
OP
amp
CCD
512 Kbyte
Sram
o High flexibilities
o Relatively simple circuit
x Large number of digital I/O pins
New Generation Driver System
E. Miyata et al. NIM (2001)
Sample Waveform
E-NA System with SSCE Integration
Board
55Fe
Spectrum (ASCA grades
02346)
Counts
readout noise
3e- rms
Energy [keV]
Spectrum (Log Scaled)
Counts
55Fe
Energy [keV]
Summary of EM CCDs
Q.E. (grade02346)
@5.9 keV [%]
Depletion
Layer [µm]
ΔE (grade 02346)
[eV] @5.9keV
epitaxial1
12±0.7
4
142±5.8
epitaxial2
37±0.8
14
152±3.1
epitaxial3
56±1.0
25
143±2.2
epitaxial4
73±1.5
42
149±1.9
bulk1
79±1.6
48
208±4.7
bulk2
57±1.2
27
143±3.2
bulk3
71±1.5
40
162±2.5
• Achieve 40 µm for epitaxial CCD and bulk CCDs in low dark
current mode (voltage of vertical transfer gate is 4 V)
• To achieve thick depletion layer and good energy resolution,
epitaxial4 or bulk3 chips will be selected for flight devices
Summary
• We have developed the engineering models for
– SSC CCDs
– SSC analog electronics
– SSC digital electronics
– SSC cooling system
All components function well.
We are now ready to construct the flight models.
• We have developed the DAQ system with low-noise,
high flexible, high speed
– achieve 3e- rms readout noise including CCD
– achieve ~40 µm depletion layer in low dark mode
Near Future Plan
• Radiation damage test is now performing
• Flight design will be fixed in this summer
• Thermal and mechanical test will be performed in the
end of this year
SSC… First X-ray CCD Camera
All Fabricated in Japan
• We, the Japanese X-ray CCD team, have developed
(just started to construct) X-ray CCD camera onboard
– ASCA (SIS)
– ((( Astro-E ))) ((((( XIS )))))
– Astro-E II ( XIS II )
• We developed neither CCD chip nor analog electronics
• We like and need to develop all for X-ray CCD for the
future mission (carry CCD, I do hope !)
• This is the first time to develop all for X-ray CCD
camera
• For success of our mission, we need to develop
CCDs having high Q.E. and high E/DE
AE having low noise capability
AE to maximize the CCD performance