Transcript ppt

Power Analysis of
WEP Encryption
Jack Kang
Benjamin Lee
CS252 Final Project
Fall 2003
Outline
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Background and Motivation
Objective
Theory
Experimental Methodology
Experimental Results
Conclusions
Future Work & Directions
Questions
Background and Motivation (1/4)
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The Digital Divide
Gap between the digitally empowered and digitally
poor, between developing and developed nations
 Can information and communication technologies
(ICT) close the gap?
 There are social AND economic reasons to solve
this problem
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Background and Motivation (2/4)
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Problems
More talk than action
 Financial sustainability
 Coordination of activities
 Scope
 E-governance
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Background and Motivation (3/4)
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Bottom of The Pyramid (BOP)
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Prahad argues that it is profitable to serve the poor
Multinational Corporations have financial incentive to step in
Prahalad, C.K. and Hammon, Allen, Serving the World's Poor, Profitably, Harvard Business Review, 9/2002.
Background and Motivation (4/4)
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So what about the technical problems?
Low-cost
 Low-power
 Intermittent Connectivity
 User Interfaces for populations with multiple
languages and low levels of literacy
 Shared accesses as a possibly dominant use
mode
 Limited skilled workforce for maintenance
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Objective
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Evaluate high-level software optimizations and
low-level hardware configurations for reducing
power dissipation applied to WEP encryption
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Provide a framework for further study in wireless
communication infrastructure for developing
regions
Theory – Loop Unrolling
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A compiler technique that extends the size of
loop bodies by replicating the body n times
The loop exit condition is then adjusted
accordingly
Why is power saved?
More efficient front end – less branches means the
fetch unit is able to fetch large blocks without being
interrupted by control decisions
 Less branches in the code means reduced power
dissipation of the branch prediction hardware
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Theory – Cache Optimizations
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Choices in associativity and block sizes will
affect the miss rate of the cache.
Power can be saved if we can reduce the miss
rate.
No need to go off chip
 Better performance means we may be able to
lower the clock frequency (and thus voltage levels)
and still meet minimum performance needs
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Experimental Methodology
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Software WEP encryption
Software is cheaper (low-cost)
 Easier to upgrade (limited maintenance)
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SimpleScalar
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Simulates hardware and software configurations
Wattch
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Provides power estimation
Wired Equivalent Privacy (1/3)
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Overview
802.11 wireless standard
 Provides wireless network with security equivalent
to wired network
 Confidentiality
 Access Control
 Data Integrity
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Wired Equivalent Privacy (2/3)
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Encryption
Hirani, Sohail A. Energy Consumption of Encryption Schemes in Wireless Devices. Master’s Thesis. University
of Pittsburgh, April 2003.
Wired Equivalent Privacy (3/3)
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Decryption
Hirani, Sohail A. Energy Consumption of Encryption Schemes in Wireless Devices. Master’s Thesis. University
of Pittsburgh, April 2003.
SimpleScalar (1/2)
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Baseline Simulation - Microprocessor
In-order issue
 No branch prediction
 Minimal number of functional units
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Integer ALU
Floating Point ALU
Integer Multiplier/Divider
Floating Point Multiplier/Divider
SimpleScalar (2/2)
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Baseline Simulation – Memory
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L1 Instruction Cache
 16-KB cache
 32-byte blocks
 Full associativity
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L1 Data Cache
 16-KB cache
 32-byte blocks
 4-way associativity
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Unified L2 Cache
 18-KB cache
 32-byte blocks
 4-way associativity
Wattch (1/2)
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Overview
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Framework for analyzing and optimizing
microprocessor power dissipation at the
architectural level
Wattch v1.02
SimpleScalar Interface
 Simulated PISA instruction set
 Built on Pentium 4/x86 platform
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Wattch (2/2)
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Conditional Clocking Styles
 NCC – No conditional clocking
 CC1 – Simple conditional clocking
 Zero power dissipation with zero accesses
 CC2 – Aggressive conditional clocking (ideal)
 Linear power dissipation with fractional accesses
 CC3 – Aggressive conditional clocking (non-ideal)
 15% power dissipation with zero accesses
Experimental Results (1/3)
Cache Associativity (2/3)
Cache Associativity (3/3)
Conclusions
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Significant power savings from software and
hardware optimizations
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Loop Unrolling
 Max = 17% reduction
 Median = 15.9% reduction
 Mean = 15.9% reduction
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Cache Associativity
 Max = 12.5% reduction
 Median = 4% reduction
 Mean = 5% reduction
Future Work & Directions
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Study combined effects of optimizations
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Apply these optimizations for new microprocessor
configurations
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Apply these optimizations to a larger test suite
References
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David Brooks, Vivek Tiwari, and Margaret Martonosi, Wattch: A Framework
for Architectural-Level Power Analysis and Optimizations, 27th International
Symposium on Computer Architecture (ISCA), June 2000.
Doug Burger and Todd M. Austin, The SimpleScalar Tool set, Version 2.0,
Computer Architecture News, pages 13-25, June 1997.
Sohail Hirani, Energy Consumption of Encryption Schemes in Wireless
Devices, Master’s Dissertation, University of Pittsburgh, 2003.
Kenneth Keniston, Grassroots ICT projects in India: Some Preliminary
Hypotheses, ASCI Journal of Management 31(1&2), 2002.
C.K. Prahalad and Allen Hammon, Serving the World's Poor, Profitably,
Harvard Business Review, September 2002.
C.K. Prahalad and Stuart L. Hart, The Fortune at the Bottom of the Pyramid,
strategy+business, issue 26, 2002.
SimpleScalar toolset. http://www.simplescalar.com
Wattch toolset. http://www.ee.princeton.edu/~dbrooks/wattch-form.html
Questions
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Any Questions?