Key Objectives of P1801

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Transcript Key Objectives of P1801

IEEE P1801 Working Group
(Unified Power Format – UPF)
Status
Stephen Bailey
Chair, P1801 Working Group
P1801 6-Apr-16
Agenda
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Quick Background
Key Technical Objectives of P1801
IEEE P1801 Schedule
Q&A
P1801 6-Apr-16
UPF Background
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Initiated by users at DAC 2006
Accellera sponsorship Sep 2006
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Donations from several companies
Atrenta, Magma, Mentor, Synopsys, TI
Accellera approves v1.0 of UPF Feb
2007
IEEE WG approved May 2007
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UPF version 2.0
P1801 6-Apr-16
Key Objectives of P1801 (v2.0)
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As with any 1.0 version, there are bugs
and ambiguities
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Discovered by vendors while implementing
tool support
By users working through “paper
prototypes” of how they would use UPF for
their design needs
Enhancements to (better) address
needs missed in v1.0
P1801 6-Apr-16
Highlights of P1801
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Better support for soft IP & incremental
refinement of low power specification
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“Command layering” for incremental
specification
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Allow multiple calls to same command with
each call adding more, but not contradictory,
information
Enhanced retention specification
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Save and restore are functions defined in
terms of one or more signals
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Highlights of P1801 (2)
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Enhanced power state information
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Consistent with incremental refinement
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Planned deferment of details (placeholders)
Can be specified prior to having a completed supply
network specified for implementation
More information for verification and analysis
as well as more complete information for
optimizing implementation
Transitions as well as states
Defined access to state information from HDLs
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Allows reference to states and triggering on state
changes in TB & within assertions
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Support for Bias
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Bias supplies
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N-well, P-well, Deep-N-Well and Deep-P-Well
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With defaults for each
New semantic definition: “corrupt-on-change”
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A power state can be attributed with this semantic
specification
Represents a bias voltage threshold that has
uncharacterized performance
Nets and registers retain current value
But are corrupted on any change while in this
state
Emulates that switching will occur but with an
unknown timing
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Enhanced Semantic Specification
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Improved semantic specification for
set_related_power_pin
(Name may change.)
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Simulation semantics specified as well as
implementation
When used on input, has semantic of a
constraint for the source connected to the
input
Merge power domains
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P1801 Schedule
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Weekly telecons (Tues mornings)
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Monthly Face to Face Meetings
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15-17 Jan: Magma hosted in SJ
25-27 Feb: Infineon hosted in Munich
18-20 Mar: Synopsys hosted in Mountain View
Draft standard for WG review:
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Except for weeks with F2F meetings
May begin 2nd set of weekly telecons to focus on technical
issues to wrap-up
Feb 2008
Enter IEEE ballot:
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End of Mar 2008
Complete balloting May/June 2008
P1801 6-Apr-16
Contact Information
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[email protected]: Email reflector
www.accellera.org/apps/org/workgroup/
p1801
Chair: [email protected]
+1 30 37 75 16 55
P1801 6-Apr-16