Transcript Metastability

Asynchronous Input Example
• Program counter normally increments, jumps to address
of interrupt subroutine on asynchronous interrupt
• How many states can Jump/Increment have?
Jump
Program
Counter
Interrupt
Increment
Clock
F. U. Rosenberger, Washington University
Asynchronous Input Example –
Revised
Jump
Program
Counter
Interrupt
Increment
Clock
• Did we solve the problem? Why not?
F. U. Rosenberger, Washington University
Metastability
Metastable State – signal not 1 or 0 or
oscillating for a nondeterministic length of time
Can occur when insufficient energy is applied to cause a
latch to switch to either a 1 or 0.
Examples:
•Dual processor with shared memory
•FIFO with asynchronous input and output
•Processor interrupts
•Yellow traffic light
•Two people meet in hallway
•Dog midway between two food dishes may starve
Altera Application Note 42
Design Approach Where Metastability
Present
• Don’t look for solution, there is none (don’t believe
everything you read). Bottom line - Can’t guarantee
correct operation with arbitrary clock and data phase
• Do design such that worst case probability of error is
acceptable
• Do understand and be able to identify trouble spots in
design
F. U. Rosenberger, Washington University
Why Metastability is a “Special”
Problem, Charles E. Molnar
• Because it “breaks most of the conceptual and
computatonal tools that we use from day to day (e.g.,
binary or two state circuits)
• It defies careful and accurate measurements
• It can produce failures that leave no discernable
evidence
• It can cause failures in systems whose software is
“correct” and whose hardware passes all conventional
tests
• It involves magnitudes of time and voltage for removed
from our daily experience
F. U. Rosenberger, Washington University
Metastability in D Flip-Flops
For D Flip-Flop, caused by setup or hold-time violations
Altera Application Note 42
Analyzing Metastability
Mean Time Between Failure (MTBF) for a synchronization
flip-flop can be estimated with the following formula
e(C2 tMET )
MTBF 
C1  fCLOCK  f DATA
where
fCLOCK is the system clock frequency
fDATA is the data transfer frequency
tMET is the additional time allowed for the flip-flop to settle
C1 and C2 are device specific parameters found by
plotting the natural log of MTBF versus tMET and
performing linear regression analysis on the data
Altera Application Note 42
MTBF vs. TMET
C2 
ln( MTBF )
tMET
e(C2 tMET )
C1 
MTBF  fCLOCK  f DATA
Altera Application Note 42
Metastability Test Circuit
Circuit that can be used to count metastable events
Altera Application Note 42
Determining TMET for a given MTBF
From test circuit we can find C2
ln( MTBF )
C2 
tMET
Then we can solve for C1
e(C2 tMET )
C1 
MTBF  fCLOCK  f DATA
With C1 and C2 known, can find required tMET for given clock
and data rates and required MTBF.
tMET 
ln( MTBF  f CLOCK  f DATA  C1 )
C2
Altera Application Note 42
Application Example
Example
Altera Flex 10K
C1 = 1.01 x 10-13, C2 = 1.268 x 1010
For one year (~3x107 seconds) and a data frequency of
2MHz and a clock frequency of 10 MHz
tMET
ln(3 107 )  ln[(10 106 )(2 106 )(1.0110 13 )

 1.41 ns
10
1.268 10
Small increases in tMET dramatically affect the MTBF.
A tMET delay to 1.59 ns increases MTBF to 10 years.
Altera Application Note 42
Synchronizer Circuits
Example
Metastable Output
Synchronized Output
Data
Clock
tMET is the clock period minus the setup time and wiring
delays (and combinational logic delays if there is logic
between the flip-flops).