Transcript This is an Instructor Guide page!

Agenda
DAY
2
Synopsys 60-I-032-BSG-005
4
S-Parameters and Linear Analysis
5
Transmission Lines and Field Solver
6
IBIS
© 2007 Synopsys, Inc. All Rights Reserved
6- 1
Unit Objectives
After completing this unit, you should be able to:

Describe what IBIS models are

Use IBIS models
6- 2
What is IBIS?
IBIS = I/O Buffer Information Specification

IBIS is a standard for describing the analog behavior
of the buffers of digital devices using plain ASCII text
formatted data

IBIS files are not really models; they contain the data
that will be used by the simulation tools behavioral
models and algorithms

IBIS started in the early 90’s to promote tool
independent I/O models for system level signal
integrity work
http://www.eigroup.org/ibis/
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3
IBIS Model Characteristics

Fast simulation:


V / I / t relationships for only external nodes of the entire buffer
No circuit detail involved:

Not useful for circuit designers

Ideal for system level interconnect design

Hides process and IP

Package modeling

Electrical Board Description

Multi-stage buffer:

[Driver Schedule]
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4
IBIS Buffers

A basic IBIS model consists of:

Four I-V curves





Two ramps
 dV/dt_rise
 dV/dt_fall
Die capacitance
 C_comp
Packaging


Pullup & POWER clamp
Pulldown & GND clamp
RLC values
For each buffer on a chip
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IBIS Buffer Block Diagram
6- 10
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Buffer Output Model
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IBIS Model I-V Curves (1/2)


[Pulldown] referenced to [Pulldown Reference]:

Contains the difference of drive and receive (3-state)
model I-V curves for driver driving low

Origin of the curve is usually 0V for normal CMOS
buffers
[Pullup] referenced to [Pullup Reference]:

Contains the difference of drive and receive (3-state)
model I-V curves for driver driving high

The origin of the curve is usually the supply voltage (Vcc
or Vdd)
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8
IBIS Model I-V Curves (2/2)


[GND Clamp] referenced to [GND Clamp Reference]:

Contains the receive (3-state) model I-V curves

The origin of the curve is usually 0v (GND) for normal CMOS
buffers
[Power Clamp] referenced to [Power Clamp Reference]:

Contains the receive (3-state) model I-V curves

The origin of the curve is usually at the supply voltage (Vcc or
Vdd)
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IBIS I-V Curve Rules of Thumb

Generally, I-V curves will be from –Vdd to
2*Vdd:

The theoretical max overshoot due to full
reflection is 2X the signal swing

Current is positive when flows into the device

GND Clamp range is –Vdd to Vdd

Power Clamp range is Vdd to 2*Vdd
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Ramp and V-t Curve Measurements

The [Ramp] and [Rising Waveform], [Falling
Waveform] keywords describe the transient
characteristics of the buffer:

Information on how fast the pullup and pulldown transistors
turn on and off with respect to time

Die capacitance (C_comp) is included

Package effects are not included
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Schematic of an I/O Circuit

Example of a simple link simulation using I/O
buffer

IBIS Buffer model used to replace transistors

W-element used to model transmission line
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IBIS Buffer Basic Syntax
BufferName node1 node2 …nodeN
+ file=‘/fullpath/file.ibs’
+ model=‘modelName’

Number of nodes depends on types of buffer

Node sequence is predefined for each supported
buffer type
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Supported Buffer Types and Syntax (1/2)

Input buffer
B_INPUT nd_pc nd_gc nd_in nd_out_of_in

Output buffer
B_OUTPUT nd_pu nd_pd nd_out nd_in [nd_pc nd_gc]

TrBi-state buffer
_3STATE nd_pu nd_pd nd_out nd_in nd_en [nd_pc nd_gc]

Input/Output buffer
B_IO nd_pu nd_pd nd_out nd_in nd_en V_out_of_in [nd_pc nd_gc]

Input ECL Buffer
B_INPUT_ECL nd_pc nd_gc nd_in nd_out_of_in

Output ECL Buffer
B_OUTPUT_ECL nd_pu nd_out nd_in [nd_pc nd_gc]

Tristate ECL Buffer
B_3STATE_ECL nd_pu nd_out nd_in nd_en [nd_pc nd_gc]
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Supported Buffer Types and Syntax (2/2)

Input-Output ECL Buffer


Terminator Buffer


B_SER_SW nd_in nd_out
Open Drain, Open Sink, Open Source Buffers




B_SERIES nd_in nd_out
Series Switch Buffer


B_TERMINATOR nd_pc nd_gc nd_out
Series Buffer


B_IO_ECL nd_pu nd_out nd_in nd_en nd_out_of_in [nd_pc nd_gc]
Same as output buffer
Open drain and open sink buffers do not include pull-up circuitry but, always
specify nd_pu
Open source buffers do not include pull-down circuitry but, always specify nd_pd
I/O Open Drain, I/O Open Sink, I/O Open Source Buffers



Same as input-output buffer
I/O open drain and I/O open sink buffers do not include pull-up circuitry but,
always specify nd_pu
I/O open source buffers do not include pull-down circuitry but, always specify
nd_pd
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BUFFER Keyword
buffer = {buffer_number | buffer_type}

Buffer numbers

















INPUT = 1
OUTPUT = 2
INPUT_OUTPUT = 3
THREE_STATE = 4
OPEN_DRAIN = 5
IO_OPEN_DRAIN = 6
OPEN_SINK = 7
IO_OPEN_SINK = 8
OPEN_SOURCE = 9
IO_OPEN_SOURCE = 10
INPUT_ECL = 11
OUTPUT_ECL = 12
IO_ECL = 13
THREE_STATE_ECL = 14
SERIES = 15
SERIES_SWITCH = 16
TERMINATOR = 17
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BUFFER Keyword Example

Examples:
b2 nd_pu nd_pd nd_out nd_in nd_pc nd_gc
+ file = '.ibis/at16245a.ibs‘
+ model = 'AT16245_OUT‘
+ buffer = 2
b2 nd_pu nd_pd nd_out nd_in nd_pc nd_gc
+ file = '.ibis/at16245a.ibs‘
+ model = 'AT16245_OUT‘
+ buffer = output
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TYP Keyword
typ={typ|min|max|fast|slow}
typ={0|-1|1|2|-2}



If the value of typ is either typ, min, or max, it
signifies a column in the IBIS file from which the
data is extracted:

The default is typ=typ

If min or max data are not available, typ data is used
If the value of typ is fast or slow, combinations of
0
the min and max data will be used Typ
Typ can also be set to a number
Min
-1
Max
1
Fast
2
Slow
-2
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Power On | Off


Power = On (default):

HSPICE connects buffer to power sources specified in
IBIS file

Do not connect the external nodes (nd_pu, nd_pd,
nd_pc, nd_gc) to voltage sources in the netlist

Do not use SAME external node name in different buffer
Power = Off:

Must connect the external nodes to voltage sources or
through parasitic RLC elements to simulate power and
ground bounce
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INTERPOL and NOWARN Keywords

INTERPOL:
Interpol={1|2}

The I-V and V(t) curves need to be interpolated

The recommended default interpolation method is linear
interpolation
interpol = 1


Interpol=2 uses quadratic bi-spline interpolation
NOWARN:

Suppresses warning messages from the IBIS parser

Do not use as the first keyword after the nodes list
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XV_PU and XV_PD Keywords

Enable state variable information of pullup and
pulldown nodes:
xv_pu = state_pu
xv_pd = state_pd

State variable information can be printed:
.print v(state_pu) v(state_pd)
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RAMP_FWF and RAMP_RWF Keywords

Used to select which ramp or waveform data to use from
the available data

Ramp_fwf controls falling waveforms or ramp:


Ramp_rwf controls rising waveforms or ramp:


ramp_fwf= {2|1|0}
ramp_rwf= {2|1|0)
Default is ramp_fwf=2 and ramp_rwf=2:

The first two waveforms found in the model will be used

0 denotes use the ramp data specified in the model

1 denotes use one waveform:

If more than one waveform is available, the first waveform
found in the model is used
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FWF_TUNE and RWF_TUNE Keywords


Control the algorithm for processing ramp and
waveforms:

Default value is 0.1

Value range is from 0 to 1
Used only if ramp_fwf and ramp_rwf are 0 or 1:
fwf_tune = fwf_tune_value
rwf_tune = rwf_tune_value
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C_Comp

C_comp normally is connected between the output
pin (input pin for input buffers)

C_comp can be split between the pullup, pulldown,
power and ground clamps using the keywords:


c_com_pu=<value>
c_com_pd=<value>

c_com_pc=<value>
c_com_gc=<value>
If C_comp is split between the pullup, pulldown,
power and ground clamps and the total exceeds
the C_comp value specified in the IBIS model,
HSPICE will continue the simulation and not give a
warning
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IBIS Buffer Scaling Keywords

All I-V and V-t curves can be scaled:





Default for all scaling factors is 1
Values must be greater than 0
I-V curves scale buffer strength
V-t curves scale buffer delay, rise and/or fall time
Pullup and pulldown scaling factors:
pu_scal=<value>

Power and ground clamp scaling factors:
pc_scal=<value>

gc_scal=<value>
Rising and falling waveform scaling factors:
rwf_scal=<value>

pd_scal=<value>
fwf_scal=<value>
Supply voltage variation scaling factors:
spu_scal=<value>
spd_scal=<value>
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HSP_VER Keyword

The default is the current version of the HSPICE
simulator

Use to set to previous version of the IBIS buffer

Syntax
hsp_ver = hspice_version
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Using the .IBIS Command (1/2)

A buffer is added to the netlist for every pin

Follows the signal_name and model_name defined
in the [Pin] list of the IBIS file


Buffers not created for POWER, GND or NC pins
The .IBIS command creates new buffers in the
netlist

Buffer_name = ‘cname’_‘pin_name’’


Cname is defined in the .ibis card in the netlist
Pin_name is defined by the [Pin] keyword in the .ibs file
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.IBIS Command Syntax (2/2)

Buffer pin names

Die side output node, if package model used:
'cname'_'pin_name'_o

Output node or input node for input buffers:
'cname'_'pin_name'

Enable node for buffers with enable pins:
'cname'_'pin_name'_en

Input node or outofin node for input buffers:
'cname'_'pin_name'_i

Outofin node for buffers other than input buffers:
'cname'_'pin_name'_outofin
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.IBIS Command Syntax (1/2)
.IBIS cname
+ file=‘file_name’
+ component=‘component_name’
+ package=[3|0|1|2|]
+ pkgfile=‘pkg_file_name’
+ <optional keywords>


Keywords

Cname - Instance name of the .IBIS command in the netlist

File_name - IBIS model file name

Component - define using the [Component] keyword in the IBIS
model file
Note: The component name and file name are case-sensitive
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.IBIS Command Syntax (2/2)

Package – (optional, default is 3) defines package parasitics to be
added to each pin

0 - does not use package parasitics

1 - use [Package] definition from the IBIS model file

2 - use [Pin] definition from the IBIS model file

3 – use the [Package Model] if it is defined in the IBIS model file

If [Package Model] is not defined, the [Pin] model will be used
If [Pin] is not defined, the [Package] model will be used

Package Model can be defined in either the IBIS file or the PKG file


Pkgfile – defines file containing package model file


Required if package model is not defined in the IBIS model file
Optional Keywords – any valid B-element optional keyword
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.IBIS Command Examples

Examples:
.ibis memory
+ file = ’dram.ibs’
+ component = ’SIMM’
+ package = 2
.ibis p_test
+ file = ‘comp.ibs’
+ component = ‘cpu_133mhz_ff’
+ package = 3
+ pkgfile = ‘test.pkg‘
+ typ=typ nowarn
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Using the .PKG Command (1/2)

Syntax
.PKG pkgname
+ file = ’pkgfilename’
+ model = ’pkgmodelname’

Where

Pkgname – package card name

Pkgfilename – name of the .pkg or .ibs file that contains
package models

Pkgmodelname – package model defined by [Define
Package Model] in the .pkg file or [Package Model] in the
.ibs file
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Using the .PKG Command (2/2)

Example:
.pkg fp1
+ file=‘ddr2tst.pkg
+ model=‘flatpack1’

The .PKG command automatically creates a series of
either lumped RLCs or distributed RLCs

Package pin names

Nodes on the die side:
’pkgname’_’pinname’_dia

Nodes on the pin side:
’pkgname’_’pinname
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Using the .EBD Command

Describes a PCB or substrate that can contain components or
other boards through a set of user visible pins

The Electrical Board Description (EBD) file describes the
electrical connectivity

The .EBD command is used in conjunction with the .IBIS
command because the EBD file contains the reference
designator of the component

HSPICE automatically creates lumped RLCs or W-elements to
express the paths

Examples of use:




SIMM, DIMM Modules
MCMs
Processor Modules
Packages
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.EBD Command Syntax
.EBD ebdname
+ file = ’ebd_filename’
+ model = ’ebd_modelname’
+ component = ’ibisname:reference_designator’
+ <component = ’ibisname:reference_designator’> …


Keywords

Ebdname – ebd card name

Ebd_filename – name the .ebd file that contains the board description

Ebd_modelname – ebd model defined by [Begin Board Description] in
the .ebd file

Ibisname - Name of the associated .IBIS command to identify IBIS
buffer component

Reference_designator - Reference designator from the node
subparameter of the [Path Description] in the ebd file
Note: The filename and modelname are case sensitive
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.EBD Example
.ebd mb1
+ file = ’memsimm.ebd’
+ model = ’16X8 SIMM’
+ component = ’mem:u21’
.ibis mem
+ file = ’mem16x8.ibs’
+ component = ’SIMM’
+ package=3
+ pkgfile=‘fpsim.pkg’

Pin names

Pins associated with the board will be named
ebdname_pin_name

Where

Pin_name is the pin name given in the [Pin Description] of the ebd
file
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EBD Example
Example from IBIS 4.0 specification
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EBD Limitations

No coupling between paths

No correct modeling of differential signaling

Transmission line parameters have to be derived
with respect to well defined reference planes

Insufficient connector modeling
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Using the .ICM Command

ICM = IBIS Interconnect Modeling Specification

“Interconnect” can be connector, cable, PCB traces or
even an IC package


Defines structure as path between “sections”
Defines the electrical data for each section
Described by
[Begin ICM Model]
…
(path description)
…
[End ICM Model]
Described by
[Begin ICM Section]
…
(RLGC or S-params)
…
[End ICM Section]
Connector
T-line
Connector
Stub
T-line
Connector
Stub
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ICM Structure (1/2)


Header Information

[Begin Header] and [End Header] keywords

Spec. Version

Filename and Revision

Date

Source, Notes, Disclaimer and Copyright
ICM Family

Description of model “family” or group

List of models in the “family”
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ICM Structure (2/2)

ICM Model Description



Type (SLM, S-parameter, MLM_*, etc.)
Signal-to-ground ratio & (optionally) reference Z
Tree Path Description




Nodal Path Description



Links groups of signals through cascaded “sections” of
model data
Describe one-to-one connections between sections and
ports or endpoints of the interconnect
Allows “forks” with same number of conductors
Links sections of model data through input & output nodes
per section
Connections need not be one-to-one
– Allows internal “dangling nodes”
Nodal and Tree Path Descriptions are mutually exclusive
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Additional ICM Constructs

ICM Pin Map


ICM Node Map


Maps connector pins to Tree Path Descriptions
Maps connector pins to Nodal Path Descriptions
ICM Section

Data block for model sections

Data is in RLGC matrix or S-parameter format



Matrices include self-inductance, capacitance,
conductance, loss, etc.
Similar format to IBIS package models
Each section is referenced by at least one Tree or Nodal
Path Description
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ICM Swath

Allows minimal, economical description to be used
for larger connectors or interconnects


Smaller electrical parameter matrices can be repeatedly
mapped over a larger structure
Includes the [ICM Swath Description] and [ICM
Swath Pin Numbers] keywords
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.ICM Syntax
.icm icm_name
+ file=‘filename.icm'
+ model=‘xxx‘
+ <swath = 1/2/3>

Keywords
 File – specify particular ICM file to include
 Model – specify which model in the file
 Swath – indicate which method is used to expand
swath matrix
1.
2.
3.
Centering the swath around the pins of interest
Expand and Centering - Expanding the swath matrix into a
larger swath matrix, centering both swaths about the paths
of interest
Expand to full sized interconnect
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.ICM Example

Example:
.icm icmtreemodel
+ file = 'test_001.icm'
+ model = 'dynamite'
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Multi-Lingual Model Support (1/2)

Supports SPICE or Verilog-A buffer model

Syntax:
B_SPICE node1 node2 node3 …
+ file='ibis_filename' model='model_name'
+ [nd_in=node_input]
+ [nd_en=node_enable]
+ [nd_outofin=node_out_of_in]
+ [typ={typ|min|max}] [power={on|off}]
+ [nowarn]
+ [para_begin para1=value1 para2=value2 …
para_end]
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Multi-Lingual Model Support (2/2)

Buffer element nodes must map port names
declared in [Ports] of [External Model]

The file of subcircuit listed in [Corner] of
[External Model] must be manually included in
netlist if the subcircuit is used by external model

Keywords para_begin and para_end are used to
assign values to parameters which are declared
in [External Model] with Verilog-A language
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Example
bspice Dri Out Vcc 0 Ven Rcv
+ file= 'extmdlva.ibs'
+ model= 'vatest'
+ nd_in=PlsV
+ nd_en=Vcc
+ nd_outofin=Oti
+ typ = typ
+ power=off
.ibs file(extmdlva.ibs) example
;
[External Model]
Language Verilog-A(MS)
;
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Component Calls for [External Circuit]

Support component calls for SPICE or Verilog-A
formatted [External Circuit]

[External Circuit] is used to describe either buffer
(similar to [External Model]) or interconnection
inside component

The naming rule to probe a die node declared in
Port_map of [Circuit Call] in a interconnection
description:
‘cname’_’die_node_name’
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Name Limit Extension

The limit on IBIS filenames has been extended to
44 characters from the existing 24 characters

The model and signal name limit has been
extended to 40 characters from the existing 20
characters
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Lab 6: IBIS Buffers
45 minutes
During this lab, you
will use IBIS buffers
and a transmission
line to do a simple
signal integrity
analysis.
IBIS buffers
Transmission line
Signal Integrity analysis
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