Transcript Lecture 2: Dynamic and static power in CMOS

Low-Power Design and Test
Dynamic and Static Power in CMOS
Vishwani D. Agrawal
Srivaths Ravi
Auburn University, USA
Texas Instruments India
[email protected]
[email protected]
Hyderabad, July 30-31, 2007
http://www.eng.auburn.edu/~vagrawal/hyd.html
Copyright Agrawal & Srivaths, 2007
Low-Power Design and Test, Lecture 2
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Components of Power
 Dynamic
 Signal transitions
 Logic activity
 Glitches
 Short-circuit
 Static
 Leakage
Copyright Agrawal & Srivaths, 2007
Ptotal =
Pdyn + Pstat
Ptran + Psc + Pstat
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Power of a Transition: Ptran
Ron
VDD
ic(t)
vi (t)
vo(t)
CL
R = large
Ground
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Charging of a Capacitor
R
t=0
v(t)
i(t)
C
V
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
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=
dq(t)/dt
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C dv(t)/dt =
[V – v(t)] /R
dv(t)
V – v(t)
───
=
─────
dt
RC
dv(t)
dt
∫ ───── = ∫ ────
V – v(t)
RC
-t
ln [V – v(t)]
=
── + A
RC
i(t)
=
Initial condition, t = 0, v(t) = 0 → A = ln V
-t
v(t) =
V [1 – exp(───)]
RC
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v(t) =
i(t)
=
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-t
V [1 – exp( ── )]
RC
dv(t)
C ───
dt
=
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V
-t
── exp( ── )
R
RC
6
Total Energy Per Charging Transition
from Power Supply
Etrans =
=
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∞
∫ V i(t) dt =
0
∞ V2
-t
∫ ── exp( ── ) dt
0 R
RC
CV2
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Energy Dissipated per Transition in
Resistance
∞2
R ∫ i (t) dt
0
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=
V2 ∞
-2t
R ──
∫ exp( ── ) dt
2
R 0
RC
=
1
─ CV2
2
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Energy Stored in Charged Capacitor
∞
∞
-t
V
-t
∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt
0
0
RC R
RC
1
= ─ CV2
2
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Low-Power Design and Test, Lecture 2
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Transition Power
 Gate output rising transition
 Energy dissipated in pMOS transistor = CV 2/2
 Energy stored in capacitor = CV 2/2
 Gate output falling transition
 Energy dissipated in nMOS transistor = CV 2/2
 Energy dissipated per transition = CV 2/2
 Power dissipation:
Ptrans =
Etrans α fck =
α fck CV2/2
α
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=
activity factor
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Components of Power
 Dynamic
 Signal transitions
 Logic activity
 Glitches
 Short-circuit
 Static
 Leakage
Copyright Agrawal & Srivaths, 2007
Ptotal =
Pdyn + Pstat
Ptran + Psc + Pstat
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Short Circuit Power of a Transition: Psc
VDD
vi (t)
isc(t)
vo(t)
CL
Ground
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Short Circuit Current, isc(t)
VDD
VDD - VTp
Vi (t)
Volt
p-transistor
starts
conducting
n-transistor
cuts-off
Vo(t)
VTn
0
Iscmaxf
isc(t)
Isc
0
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tB
tE
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Time (ns)
13
Peak Short Circuit Current
 Increases with the size (or gain, β) of
transistors
 Decreases with load capacitance, CL
 Largest when CL = 0
 Reference: M. A. Ortega and J. Figueras,
“Short Circuit Power Modeling in
Submicron CMOS,” PATMOS ’96, Aug.
1996, pp. 147-166.
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Short-Circuit Energy per Transition
 Escf =
=
∫tB
tE
VDD isc(t)dt
(tE – tB) Iscmaxf VDD / 2
 Escf =
tf (VDD - |VTp| - VTn) Iscmaxf / 2
 Escr =
tr (VDD - |VTp| - VTn) Iscmaxr / 2
 Escf = Escr = 0, when VDD = |VTp| + VTn
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Short-Circuit Energy
 Increases with rise and fall times of input
 Decreases for larger output load capacitance
 Decreases and eventually becomes zero
when VDD is scaled down but the threshold
voltages are not scaled down
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Short-Circuit Power Calculation
 Assume equal rise and fall times
 Model input-output capacitive coupling
(Miller capacitance)
 Use a spice model for transistors
 T. Sakurai and A. Newton, “Alpha-power Law
MOSFET model and Its Application to a CMOS
Inverter,” IEEE J. Solid State Circuits, vol. 25,
April 1990, pp. 584-594.
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Short Circuit Power
Psc =
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α fck Esc
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Psc, Rise Time and Capacitance
VDD
Ron
vi (t)
tf
VDD
ic(t)+isc(t)
vo(t)
CL
R = large
Ground
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vo(t)
tr
vo(t)
───
R↑
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isc, Rise Time and Capacitance
Isc(t) =
-t
VDD[1- exp(─────)]
vo(t)
R↓(t) C
──── = ──────────────
R↑(t)
R↑(t)
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Low-Power Design and Test, Lecture 2
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iscmax, Rise Time and Capacitance
i
Small C
vo(t)
Large C
vo(t)
1
────
R↑(t)
iscmax
t
tf
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Low-Power Design and Test, Lecture 2
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Psc, Rise Times, Capacitance
 For given input rise and fall times short
circuit power decreases as output
capacitance increases.
 Short circuit power increases with increase
of input rise and fall times.
 Short circuit power is reduced if output
rise and fall times are smaller than the
input rise and fall times.
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Low-Power Design and Test, Lecture 2
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Summary: Short-Circuit Power
 Short-circuit power is consumed by each
transition (increases with input transition time).
 Reduction requires that gate output transition
should not be faster than the input transition
(faster gates can consume more short-circuit
power).
 Increasing the output load capacitance reduces
short-circuit power.
 Scaling down of supply voltage with respect to
threshold voltages reduces short-circuit power;
completely eliminated when VDD ≤ |Vtp|+Vtn .
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Low-Power Design and Test, Lecture 2
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Components of Power
 Dynamic
 Signal transitions
 Logic activity
 Glitches
 Short-circuit
 Static
 Leakage
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Low-Power Design and Test, Lecture 2
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Leakage Power
IG
Ground
Gate
VDD
R
Source
Drain
n+
Bulk Si (p)
Isub
IPT
IGIDL
n+
ID
nMOS Transistor
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Leakage Current Components
 Subthreshold conduction, Isub
 Reverse bias pn junction conduction, ID
 Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
 Drain source punchthrough, IPT due to
short channel and high drain-source
voltage
 Gate tunneling, IG through thin oxide;
may become significant with scaling
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Subthreshold Current
Isub = μ0 Cox (W/L) Vt2 exp{(VGS –VTH ) / nVt }
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
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IDS for Short Channel Device
Isub= μ0 Cox(W/L)Vt2 exp{(VGS –VTH + ηVDS)/nVt}
VDS = drain to source voltage
η: a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron
Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104
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Low-Power Design and Test, Lecture 2
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Increased Subthreshold Leakage
Log (Drain current)
Scaled device
Ic
Isub
0 VTH’ VTH
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Low-Power Design and Test, Lecture 2
Gate voltage
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Summary: Leakage Power
 Leakage power as a fraction of the total power
increases as clock frequency drops. Turning
supply off in unused parts can save power.
 For a gate it is a small fraction of the total
power; it can be significant for very large
circuits.
 Scaling down features requires lowering the
threshold voltage, which increases leakage
power; roughly doubles with each shrinking.
 Multiple-threshold devices are used to reduce
leakage power.
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Technology Scaling
 Scaling down 0.7 micron by factors 2 and 4
leads to 0.35 and 0.17 micron technologies
 Constant electric field assumed
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Constant Electric Field Scaling
 B. Davari, R. H. Dennard and G. G.
Shahidi, “CMOS Scaling for High
Performance and Low Power—The Next
Ten Years,” Proc. IEEE, April 1995, pp.
595-606.
 Other forms of scaling are referred to as
constant-voltage and quasi-constantvoltage.
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Bulk nMOSFET
Polysilicon
Gate
Drain
W
Source
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
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Technology Scaling
 A scaling factor (S ) reduces device dimensions as
1/S.
 Successive generations of technology have used a
scaling S = √2, doubling the number of transistors
per unit area. This produced 0.25μ, 0.18μ, 0.13μ,
90nm and 65nm technologies, continuing on to
45nm and 30nm.
 A 5% gate shrink (S = 1.05) is commonly applied
to boost speed as the process matures.
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston:
Pearson Addison-Wesley, 2005, Section 4.9.1.
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Low-Power Design and Test, Lecture 2
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Constant Electric Field Scaling
Device Parameter
Scaling
Length, L
1/S
Width, W
1/S
Gate oxide thickness, tox
1/S
Supply voltage, VDD
1/S
Threshold voltages, Vtn, Vtp
1/S
Substrate doping, NA
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S
35
Constant Electric Field Scaling (Cont.)
Device Characteristic
Scaling
W / (L tox)
β
Current, Ids
β (VDD – Vt )
S
2
1/S
Resistance, R
VDD / Ids
1
Gate capacitance, C
W L / tox
1/S
Gate delay, τ
RC
1/S
Clock frequency, f
1/ τ
S
Dynamic power per gate, P
CV 2 f
Chip area, A
1/S
2
1/S
2
Power density
P/A
1
Current density
Ids /A
S
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Low-Power Design and Test, Lecture 2
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Problem: A Design Example


A battery-operated 65nm digital CMOS device is found
to consume equal amounts (P ) of dynamic power and
leakage power while the short-circuit power is
negligible. The energy consumed by a computing task,
that takes T seconds, is 2PT.
Compare two power reduction strategies for extending
the battery life:
A.
B.
Clock frequency is reduced to half, keeping all other
parameters constant.
Supply voltage is reduced to half. This slows the gates down
and forces the clock frequency to be lowered to half of its
original (full voltage) value. Assume that leakage current is
held unchanged by modifying the design of transistors.
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Solution: Part A. Clock Frequency
Reduction


Reducing the clock frequency will reduce
dynamic power to P / 2, keep the static
power the same as P, and double the
execution time of the task.
Energy consumption for the task will be,
Energy = (P / 2 + P ) 2T = 3PT
which is greater than the original 2PT.
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Solution: Part B. Supply Voltage
Reduction

When the supply voltage and clock frequency
are reduced to half their values, dynamic power
is reduced to P / 8 and static power to P / 2.
The time of task is doubled and the total energy
consumption is,
Energy = (P / 8 + P / 2) 2T = 5PT / 4 =1.25PT

The voltage reduction strategy reduces energy
consumption while a simple frequency reduction
consumes more energy.
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Low-Power Design and Test, Lecture 2
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