Transcript CMOS-tech-loose

CMOS Detector Technology
Markus Loose
Alan Hoffman
Vyshnavi Suntharalingam
Rockwell Scientific
Raytheon Vision Systems
MIT Lincoln Laboratory
Scientific Detector Workshop, Sicily 2005
CMOS - 1
General CMOS Detector Concept
CCD Approach
Photodiode
CMOS Approach
Photodiode
Amplifier
+
Pixel
Charge generation &
charge integration
Array Readout
Charge transfer
from pixel to pixel
Sensor Output
Output amplifier performs
charge-to-voltage conversion
CMOS - 2
Charge generation,
charge integration &
charge-to-voltage conversion
Multiplexing of
pixel voltages:
Successively
connect amplifiers
to common bus
Various options possible:
- no further circuitry (analog out)
- add. amplifiers (analog output)
- A/D conversion (digital output)
Common CMOS Features
• CMOS sensors/multiplexers utilize the same process as modern
microchips
– Many foundries available worldwide
– Cost efficient
– Latest processes available down to 0.13 µm
• CMOS process enables integration of many additional features
–
–
–
–
–
–
Various pixel circuits from 3 transistors up to many 100 transistors per pixel
Random pixel access, windowing, subsampling and binning
Bias generation (DACs)
Analog signal processing (e.g. CDS, programmable gain, noise filter)
A/D conversion
Logic (timing control, digital signal processing, etc.)
• Electronic shutter (snapshot, rolling shutter, non-destructive reads)
– No mechanical shutter required
• Low power consumption
• Radiation tolerant (by process and by design)
CMOS - 3
Astronomy Application: Guiding
• Special windowing can be used to
perform full-field science integration in
parallel with fast window reads.
 Simultaneous guide operation and science
data capture within the same detector.
• Two methods possible:
– Interleaved reading of full-field and window
• No scanning restrictions or crosstalk issues
• Overhead reduces full-field frame rate
– Parallel reading of full-field and window
• Requires additional output channel
• Parallel read may cause crosstalk or conflict
• No overhead  maintains maximum full-field
frame rate
Full field row
Window
Full field row
Full field row
Window
CMOS - 4
Full field row
Full field row
Window
Stitching Enables Large Sensor Arrays
• The small feature size of modern CMOS processes limits the maximum
area that can be exposed in one step (so-called reticle) to about 22 mm.
• However, larger chips can produced by breaking up the design into
smaller sub-blocks that fit into the reticle.
– Sub-blocks are exposed one after
another
– Some blocks are used multiple
times
– Ultimate limit is given by wafer size
Stitched CMOS Sensor
horiscan1
horiscan2
V
1
array
array
array
V
2
array
array
array
V
3
array
array
array
Reticle
horiscan2
horiscan1
22mm
V
1
CMOS - 5
V V
2 3
array
Monolithic CMOS
• A monolithic CMOS image sensor combines the photodiode and the
readout circuitry in one piece of silicon
– Photodiode and transistors share the area => less than 100% fill factor
– Small pixels and large arrays can be produced at low cost => consumer
applications (digital cameras, cell phones, etc.)
3T Pixel
Reset
SF
PD
Select
Read Bus
photodiode transistors
4T Pixel
Reset
Pinned PD
p+
n+
SF
TG
n+
p-sub
Select
Read Bus
CMOS - 6
Complete Imaging Systems-on-a-Chip
• Monolithic CMOS technology has enabled highly integrated,
complete imaging systems-on-a-chip:
– Single chip cameras for video and digital still photography
– Performance has significantly improved over last decade and is
better or comparable to CCDs for many applications.
– Especially suited for high frame rate sensors (> Gigapixel/s) or
other special features (windowing, high dynamic range, etc.)
• However, monolithic CMOS is still limited with respect to
quantum efficiency:
– Photodiode is relatively shallow
=> low red response
– Metal and dielectric layers on
top of the diode absorb or
reflect light
=> low overall QE
– Backside illumination possible,
but requires modification of
CMOS process
• Microlenses increase fill factor:
photodiode
CMOS - 7
2 Mpixel HDTV CMOS Sensor
Quantum Efficiency of a CMOS sensor
Si PIN
NIR AR coating
Si PIN
UV AR coating
3T pixel
w/ microlenses
Sensor Chip Assembly (SCA) Structure:
Hybrid of Detector Array and ROIC Connected by Indium Bumps
Detector Array
Indium bump
Detector Array
Silicon Readout Integrated Circuit (ROIC)
Mature interconnect technique:
– Over 4,000,000 16,000,000 indium bumps per SCA demonstrated
– 99.9% interconnect yield
• Also called a Focal Plane Array (FPA) or Hybrid Array
CMOS - 8
Number of Pixels per Array
CMOS SCA Revolution
1E+09
MWIR arrays
1E+08
Moore's law with 18 month doubling time
predicted
1E+07
1E+06
1E+05
1E+04
1E+03
1E+02
1980
1985
1990
1995
2000
2005
2010
Year First used in Astronomy
• Large CMOS hybrids revolutionized infrared astronomy
• Growth in size has followed "Moore's Law" for over 20 years
– 18 month doubling time
CMOS - 9
Three Most Common Input Circuits
for CMOS ROICs
Circuit
SFD
(Source Follower per
Detector)
also called "Self
Integrator"
Advantages
•
•
•
•
simple
low noise
low FET glow
low power
CTIA
(Capacitance
Transimpedance
Amplifier)
• very linear
• gain determined by
ROIC design (Cfb)
• detector bias remains
constant
DI
(Direct Injection)
• large well capacity
• gain determined by
ROIC design (Cint)
• detector bias remains
constant
• low FET glow
• low power
CMOS - 10
Disadvantages
• gain fixed by detector
and ROIC input
capacitance
• detector bias changes
during integration
• some nonlinearity
Comments
Most common
circuit in IR
astronomy
• more complex circuit
• FET glow
• higher power
Very high gains
demonstrated
• poor performance at
low flux
Standard
circuit for high
flux
Temperature and Wavelengths of
High Performance Detector Materials
Si PIN
InGaAs
SWIR HgCdTe
MWIR HgCdTe
InSb
LWIR
HgCdTe
Si:As IBC
Approximate detector temperatures for dark currents << 1 e-/sec
CMOS - 11
Detector Material Choices for CMOS Hybrid Arrays
Detector
Material
Spectral
Range*, m
Operating
Temp***, K
Si PIN
0.4 – 1.0
~ 200
InGaAs
0.9** – 1.7
~ 130
HgCdTe:
1.7m
2.5 m
5.2 m
10 m
InSb
Si:As IBC
(BIB)
0.9** – 1.7
0.9** – 2.5
0.9** – 5.2
5 – 10
General Comments
• All detectors can have:
– 100% optical fill factor
– 100% internal QE (total QE
depends on AR coat)
• Exception: Si:As is 40-70%
between 5 and 10 m
~ 140
~ 90
~ 50
~ 25?
0.4 – 5.2
~ 35
5 – 28
~7
• ROICs are interchangeable
among detectors (except Si:As)
• HgCdTe and InGaAs require
special packaging due to CTE
mismatch between detector and
ROIC
* Long wave cutoff is defined as 50% QE point
** Spectral range can be extended into visible range by removing substrate
*** Approximate detector temperatures for dark currents << 1 e-/sec
CMOS - 12
Process Comparison
CCD
CMOS
> 35 years of evolution
“Trailing edge” fabs
Economics of scale accelerate progress
Lower fabrication cost, Foundry access
High resistivity (deep depletion) substrates
Controlled temperature ramps & stress control
Epi doping optimized for digital CMOS
Scalable to 300mm
Buried channel
Multiple oxidation cycles
Complex implant engineering
Rapid Thermal Processing (RTP)
Single gate dielectric thickness
Multiple gate dielectric thicknesses
Doped polysilicon (single type)
Complementarily doped polysilicon
Silicided polysilicon and FET source/drain
Highly nonplanar surfaces
Conservative design rules
Fine-line patterning
Multiple metal layers (dense routing)
Vulnerable to space-radiation-induced traps
Highly suitable for long-term space-based
applications
2m
2m
Four-Poly OTCCD
CMOS - 13
180-nm SRAM cell
2m
Stacked via to poly
Limitations of Standard Bulk CMOS APS
Pixel Layout
• Fill factor tradeoff
– Photodetector and pixel transistors share
same area
– PD from Drain-Substrate or Well-Substrate
diode
photodiode
OUT
• Low photoresponsivity
– Shallow, heavily doped junctions
– Limited depletion depth
– Absorption and reflection in poly, metal, and
oxide layers
– Surface recombination at Si/SiO2 interface
– QE*FF > 60% is good, many < 20%
• High leakage
– LOCOS/STI, salicide
– Transistor short channel effects
RST
VDD
ROW
VDD
ROW
n+
p-well
• Substrate bounce and transient coupling
effects
p-epi
p+ Substrate
CMOS - 14
OUT
RST
Field Oxide
n-Well
p+
Advantages of Vertical Integration
Addressing
Conventional Monolithic APS
3-D Pixel
Light
PD
pixel
PD
3T
pixel
ROIC
Processor
Addressing
A/D, CDS, …
• Pixel electronics and detectors
share area
• Fill factor loss
• Co-optimized fabrication
• Control and support electronics
placed outside of imaging area
• 100% fill factor detector
• Fabrication optimized by
layer function
• Local image processing
– Power and noise
management
• Scalable to large-area focal
planes
CMOS - 15
Approaches to 3D Integration
(To Scale)
Tier-1
3D-Vias
3D-Vias
10 m
Tier-2
10 m
Photo Courtesy of RTI
Bump Bond used to
flip-chip interconnect
two circuit layers
CMOS - 16
10 m
Two-layer stack using
Two-layer stack with
insulated vias through Lincoln’s SOI-based vias
thinned bulk Si
Comparison CMOS vs. CCD for Astronomy
Property
CCD
Hybrid CMOS
Resolution
> 4k x 4k
2k x 2k in use, 4k x 4k demonstrated
Pixel pitch
10 – 20 µm
18 – 40 µm, < 10 µm demonstrated
Typ. wavelength
coverage
400 – 1000 nm
400 – 1000 nm with Si PIN
400 – 5000 nm with InSb or HgCdTe
Noise
Few electrons
Few electrons with multiple sampling
Shutter
Mechanical
Electronic, rolling shutter
Power Consumption
High
Typ. 10x lower than CCD
Radiation
Sensitive
Much less susceptible to radiation
Control Electronics
High voltage clocks, at Low voltage only,
least 2 chips needed
can be integrated into single chip
Special Modes
Orthogonal Transfer,
Binning,
Adaptive Optics
Windowing, Guide Mode,
Random Access, Reference Pixels,
Large dynamic range (up the ramp)
Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a
number of significant advantages, specifically for large mosaic focal plane arrays.
CMOS - 17