Transcript i B - Muhazam

ECA1212
Introduction to Electrical &
Electronics Engineering
Chapter 5: Bipolar Junction Transistor
by Muhazam Mustapha, October 2011
Learning Outcome
By the end of this chapter students are
expected to:
• Be able to explain some basic physical
theory and operation of BJT
• Be able to do calculation on DC and AC
analysis on BJT circuit
Chapter Content
•
•
•
•
Theory of BJT
BJT Operation
DC Analysis
AC Analysis
Bipolar Junction Transistor
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Bipolar Junction Transistor
• If diodes are made by fabricating one PN
junction, BJT are made by fabricating two PN
junctions.
• It involves fabrication of 3 layers of P-N-P (pnp)
or N-P-N (npn) types:
• The middle layer has to be
very thin
• 3 terminals are attached to
the 3 layers
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p
n
n
p
p
n
Terminals
• The middle layer is called BASE (B)
• The top and bottom layers are not symmetrical
• Top layer is called COLLECTOR (C) – doped
more lightly than the bottom layer (emitter)
• Bottom layer is called
EMITTER (E) – doped
more heavily than the top
layer (collector)
Collector
Collector
p
Base
n
n
Base
p+
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Emitter
p
n+
Emitter
Circuit Symbol and Notations
• pnp BJT symbol:
• npn BJT symbol:
C
B
C
B
E
C
B
E
C
B
E
• The direction of the arrow is the direction of
the current when the BE junction is put on
forward bias
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E
Circuit Symbol and Notations
• In normal operation, BE junction is put to
forward bias
• For that reason, npn is more popular since E
is normally put to the lowest voltage on the
BJT
• Hence, B has to be at higher voltage in order
to put BE junction in forward bias
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Circuit Symbol and Notations
• Notation for currents and voltage for npn:
+
C
vCB
iC
−
iB
+
B
vCE
+
−
iE
vBE
−
E
KCL: iE = iB + iC
KVL: vCE = vCB + vBE
• For pnp, the polarities are reversed
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Transport Phenomena
• Transistor can be considered as two diode
joined back to back with the joint at base
• Diode of BE junction is forward biased, hence
there will be current flowing
• Diode of CB junction is reverse biased, hence
there is no current
C
B
E
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Transport Phenomena
• So how do we get current flowing through C?
• Current manages to get through C due to the
fact that B layer is very thin
• Since B layer is very thin, the reversely flowing
transport (electron or hole) at BE junction will
overshoot into the depletion region on the
reverse biased CB junction
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Transport Phenomena
N
P
overshooting
electrons across
reverse biased
junction causing
large avalanche
current
hole movement
N
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forward biased
electron
movement
Transport Phenomena
• These overshot transport will further collide with
the covalence bond in depletion region and
produce more holes and electrons
• The newly produced electrons and holes will
further collide with other bonds and produce
more and more new free electrons and holes
• The whole process explained above is called
avalanche
• These avalanche produced electrons and holes
will too move under the influence of the external
field (voltage of vCE)
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Transport Phenomena
• Hence the current through C (iC) is contributed
by the overshooting and avalanched transport
• Since the overshooting current is due to iB, and
since the amount of the avalanche current is
due to the overshooting current, then the
amount of avalanche current would be
proportional to iB
• So as to say, iB actually controls iC by some
multiplication factor
• This factor is called the CURRENT GAIN, β
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I-V Characteristic
• Since iC can be controlled by iB, we can
consider BJT like an input-output transfer box
• The current and voltage input parameter of BJT
are iB and vBE respectively
• While the current and voltage output parameter
of BJT are iC and vCE respectively
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iC
INPUT
iB
+
vCE
B
+
vBE
−
−
E
OUTPUT
• The I-V characteristic
of BJT is featured by
the I-V characteristics
of these input and
output
C
BE (Input) Characteristic
• Since BE junction is just like a forward biased
diode, the I-V characteristic is so like that too
500
IB (μA)
400
300
200
100
0.1
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0.2
0.3
0.4
0.5
VBE (V)
0.6
0.7
0.8
0.9
1.0
CE (Output) Characteristic
• Since CB junction is reversed biased, the I-V
characteristic of CE is flat (zero) unless IB > 0
• With some values of IB, we get a family of I-V flattening
curves for CE
50
IC (mA)
IB = 300μA
40
IB = 250μA
30
IB = 200μA
IB = 150μA
20
IB = 100μA
10
IB = 50μA
IB = 0
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1
2
3
4
5
VCE (V)
6
7
8
9
10
Operation Region
• BJT may be put to operate at 4 different
operation mode – for our class we will be
covering only 3 modes
• The 3 modes are called operation region
• The region is defined by the areas in CE
(output) I-V characteristic graph:
• Active
• Saturation
• Cutoff
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Operation Region
SATURATION
REGION
50
IB = 300μA
IC (mA)
40
IB = 250μA
ACTIVE
REGION
30
IB = 200μA
IB = 150μA
20
IB = 100μA
10
IB = 50μA
IB = 0
1
2
3
4
5
6
VCE (V)
CUTOFF
REGION
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7
8
9
10
Cutoff State / Region
• The BJT is basically in OFF condition with no
current flowing because IB is zero
• Uses:
• OFF state in digital circuit
• OFF state for analog switch
• Detailed features:
• IB = 0
• IC = ICEO ≈ 0
• VCE ≥ 0
• VBE < VD
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Saturation State / Region
• The BJT is basically in full ON condition with
very low VCE whereby the BJT may be
considered to have a very low output resistance
• Uses:
• ON state in digital circuit
• ON state for analog switch
• Detailed features:
• IB > 0
• IC < βIB
• VCE = Vsat ≈ 0.2V
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Active State / Region
• The BJT is in linear analog amplification mode
whereby IC is almost proportional to IB
• Uses:
• Analog signal amplication
• Detailed features:
• IB > 0
• IC = βIB
• VCE > VD
• VBE = VD
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Detecting Operation Region
• It’s easy:
• If VBE < VD (means IB is 0), then the BJT is in
cutoff regardless of VCE
• If VBE = VD and VCE = Vsat, then the BJT is in
saturation
• Otherwise it is in active region – BE junction
forward biased and BC junction reverse
biased
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Biasing (DC Analysis)
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DC Analysis (Biasing)
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Chapter 10.4, Example 10.7, Example 10.9
• Biasing of a transistor means putting the
transistor’s VCE and IC into a desired position in
the IC-VCE graph
• This is done normally if we want the transistor to
operate in active region
• Cutoff and saturation region normally don’t
require much biasing since the area is limited
• The biasing process is a little tricky since IC is
controlled by IB – not directly by VCE
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DC Analysis (Biasing)
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Chapter 10.4, Example 10.7, Example 10.9
• The position of the biased BJT’s VCE and IC is
called Q point
• The value of IB is also required for the biasing
• There are a few biasing configuration exist, but
for the purpose of non-EE class, we will only
study the most popular configuration called selfbias common emitter configuration
– Refer to Giorgio Rizzoni’s Fundamentals of Electrical
Engineering Figure 10.28
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DC Analysis (Biasing)
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Figure 10.29
RB = R1 || R2
R1
IC
RC
RB
+
IB
VCE
+
VBE
R2
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−
RE
−
IC
RC
+
IB
VCE
VCC
VBB
IE
VBB = (VCC)(R2)/(R1+R2)
+
VBE
−
RE
−
IE
Thevenin’s Equivalent
VCC
DC Analysis (Biasing)
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: pages 573 – 575
• The target of biasing process is to find the value
of the resistors so that Q point is position at
around VCC/2 in the IC-VCE characteristic graph
• R1, R2 and RE will determine IB
• IB will determine IC – either by IC = βIB, or by an
IC-VCE graph
• Then from KVL, VCE = VCC−ICRC−IERE
– This equation is what called load-line equation
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DC Analysis (Biasing)
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: pages 573 – 575
Steps:
• R1 and R2 will be combined using Thevenin’s
theorem to form RB
• Use KVL on BE loop to get IB from RB and IE
• Use β or IC-VCE graph to get IC
• Use KVL on CE loop (load-line equation) with
the required VCE for the Q point to get RC
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DC Analysis (Biasing)
• Class discussion: Giorgio Rizzoni’s Principles
and Applications of Electrical Engineering:
pages 573 – 575, Example 10.9
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AC Analysis
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AC Analysis
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Example 10.8, page 570-574
• AC analysis is done to determine the
performance of transistor amplifier circuit
• There are a few parameters of interest, like
input and output resistance, but for the purpose
of non-EE class, we will do only AC gain
(current and voltage)
• AC analysis is done after biasing is completed
and assuming there is some AC signal being
introduced into the circuit as superimpose on
top of the DC values (biasing)
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AC Analysis
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Example 10.8, page 570-574
• The oscillation of the input and output signals
will be denoted by Δ (delta)
• For this class we will consider the I-V
characteristic of the sinusoidal input and output
signals will be the same as the DC relationship
– next slide
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AC Analysis
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Example 10.8, page 570-574
R1
RC
ΔVO
ΔVB
R2
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VCC
RE
AC Analysis
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Example 10.8, page 570-574
I C

I B
VO  VCE   RC I C
Output
Input
V B
I B 
RB
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Voltage
Gain
VO

VB
ΔVO Formula
Refer to Giorgio Rizzoni’s Principles and Applications of Electrical
Engineering: Example 10.8, page 570-574
In the formula for ΔVO, it only
depends on ΔIC even though
from the KVL at the output it
should also depends on ΔIE.
The reason for this is in real
circuit we put a capacitor
across RE which effectively
SHORTS circuit RE when AC
current flows – means we
can disregard RE in AC
analysis formula.
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R1
RC
ΔVO
ΔVB
R2
VCC
RE
AC Analysis
• Class discussion: Giorgio Rizzoni’s Principles
and Applications of Electrical Engineering:
pages 570 – 574, Example 10.8
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