Transcript PPT - School of Engineering and Applied Science

The George Washington University
School of Engineering and Applied Science
Department of Electrical and Computer Engineering
ECE122 – 30
Lab 3: Layout of a Buffer
Jason Woytowich
Ritu Bajpai
Modified on September 20, 2007
Objective
• Our objective today is to learn to get the
layout for our module, in L- Edit.
• For this we first design a buffer in S-Edit.
• Obtain it’s layout in L-Edit.
• Simulate the extracted view in T-Spice.
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Buffer
• What is a buffer?
• A buffer is a circuit which does not affect
the voltage of a circuit (voltage buffer) or
current of a circuit (current buffer) yet
alters the desired parameters to improve
the performance of the circuit.
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Why a buffer?
• For example a buffer can be used as an
impedance transforming state at the
output. It can be used to reduce the output
impedance of a circuit while keeping the
voltage response unchanged.
• Or a buffer can also be used as a wave
shaping stage for digital circuits.
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Layout Basics1
• Layout of the chip defines the various
layers associated with the masks used in
fabrication.
• The goal of layout process is to implement
the design in a compact area while
satisfying the design rules set by the
foundry.
1. Analysis and design of digital integrated circuits by Hodges Jackson and Saleh.
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Schematic Using S-Edit
• A buffer module is created using 2 SCMOS
inverters, placed in series and terminated on 2
sides by input and output ports as shown below.
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Creating a symbol
• Once you have your schematic ready, go
to the symbol mode for your module in SEdit and create a symbol for the buffer.
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Instantiating the buffer
• Instance your buffer into a new module
and add pads to the inputs and outputs.
• I saved this module as Buffer_wPads
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Exporting the design
• Export your design as a tpr file.
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Open L-Edit
• Open L-Edit
• Replace Setup:
C:\TannerLib\SCMOS\mhp_n05d.tpr
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Replace set up
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SPR Setup in L-Edit
• Go to SPR->Setup
• Fill in the paths for the tech library and your netlist
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SPR Place and Route in L-Edit
• Go to SPR->Place and Route, Hit Run
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Layout Using L-Edit
• If it completes correctly you will see this:
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Top view of layout with pad frame
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Note the pads on the pad frame
• We see that there are total 4 pads on the
pad frame.
• Two of them correspond to the pads that
we attached at the input and the output of
the buffer.
• Other two correspond to Vdd and Gnd.
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Zoomed in top view of the layout
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Obtaining cross-sectional view of the layout
• Cross sections
• Process Definition File is C:\Program Files\Tanner EDA\L-Edit
11.0\samples\tech\mosis\mhp_n05.xst
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Cross sectional view of the layout
•You will not see the exactly same cross-sectional view as shown above
because it depends on the co-ordinate you choose.
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Cross-sectional view
• You can choose pick option from the
cross-section window instead of defining
the co-ordinate and use the cursor to
choose the co-ordinate on top view where
you want to see the cross-sectional view.
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Choosing Pick option
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Simulating Your Layout
• Once that we have a layout we can
simulate our design with parasitic
capacitances.
• First we will draw ports over each of the
pad with Metal3 selected.
• We will give them descriptive names.
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Zoom into the top view
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Metal layers in the layout
•
•
•
•
Metal 1
Metal 2
Metal 3
You can use the drop down menu to see
the metal layers are color coded as shown
above.
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Metal layers in the layout
• Metal 1 is used for Gnd and Vdd.
• Metal 2 is used for in and out connects.
• We will use metal 3 for the ports on the
pad.
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Adding the ports
2. Click on the port option.
1. Select Metal 3 from
Drop down menu.
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Placing the ports
• Follow the metal 2 layer connecting node
in to the pad and zoom into the pad.
• Click on the port.
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Adding the ports
Click OK and
click on the pad
to drop the port
name.
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Adding the ports
• Note: You might not be able to see the
port name appear on the pad after you
place it as the text appears in black color
and you really have to zoom in to be able
to see it.
• Add ports to each out, Gnd and Vdd pad.
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Port name zoomed in!
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Simulating Your Layout
• Copy the file C:\TannerLib\tech\mosis\mhp_n05.ext into
your working directory
• Make the following modification
# Linear capacitor using Cap-Well
# device = CAP(
#
RLAYER=cap using Cap-Well;
#
Plus=poly wire;
#
Minus=ndiff;
#
MODEL=;
#
)
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Simulating Your Layout
• Go to Tools->Extract
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Simulating Your Layout
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Simulating Your Layout
• From the S-Edit window click on the T-Spice tab
to open the output in T-Spice.
• Add simulation commands and power supplies
• Replace signal names where necessary
.include "C:\Program Files\Tanner EDA\T-Spice 9.1\models\ml2_125.md"
.tran/powerup 2n 400n method=bdf
.print tran v(In,Ext_Gnd) v(Out,Ext_Gnd)
V1 Ext_Vdd Ext_Gnd 5.0
V2 In Ext_Gnd PULSE (5V 0V 0 1n 1n 50n 100n)
• I named my ports on the pads as In, Out, Ext_Gnd and Ext_Vdd.
• Node V1 has Ext_Vdd as 5V w.r.t Ext_Gnd.
• Node V2 has In w.r.t Ext_Gnd as a PULSE input whose parameters are
defined within brackets.
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Homework
• Implement the following functions as a single
module using only NAND gates from the
SCMOS library.
• Test and layout.
• Extra points for optimal designs
X = ((!A)B + A(!B)C)
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