BJT – Real Characteristics
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Transcript BJT – Real Characteristics
Plans
• How do the computed BJT I-Vs compare with expts?
• Can we understand the discrepancies?
• What does the gain look like?
• AC properties (small signal and transient response)
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Common Base
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Common Emitter
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BJT – Real Characteristics
• What’s wrong with these pictures?
• Common Base:
– Input characteristic shows VCB dependence
– Output shows breakdown at VCB0
• Common Emitter
– Input characteristic pretty good agreement
– Output characteristic:
• Upward slope in IC – quasilinear VEC dependence
• Breakdown at VCE0
• Upturn prior to breakdown
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Base Width Modulation: “Early” Effect
• Base width has been assumed to be constant
• When bias voltages change, depletion widths change and the
effective base width will be a function of the bias voltages
• Most of the effect comes from the C-B junction since the bias
on the collector is usually larger than that on the E-B junction
Base width gets smaller as applied voltages get larger
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Early Effect: Common Base Input Characteristic
IE IF 0 (e qV
EB
/ kT
1) R IR 0 (e qV
CB
/ kT
1)
Ebers-Moll
Assuming –VCB > few kT/q and W/LB << 1
IF 0
W
cosh
D
D
LB qA DB p
qA E nE 0 B pB0
B0
LE
LB
W
W
sinh
LB
IE IF 0e qV
EB
/ kT
qA
DB
pB0e qV
W
EB
/ kT
• Exponential prefactor will increase as VCB increases (W
decreases)
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Early Effect: Common Emitter Output Characteristic
IC dcIB ICE 0
dc
1
DE W N B 1 W
DB LE NE 2 LB
2
Weff W WEB Base WCB Base W WCB Base
WCB
2K S 0 N A ND
Vbi VCB
ND N A
q
WCB Base
1
2
NC
xn W Base
NC NB
• If NC << NB most of the depletion is in the collector and
modulation of base width is minimized – reduced Early Effect
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Early Voltage
IC
J M Early
VCE
VEarly
Converge ~ at single point called "Early Voltage" (after James Early)
Large "Early Voltage" = Absence of "Base Width Modulation"
= Transistor ~ immune to operating voltage changes
BUT requires wide base => lower gain
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Avalanche Multiplication Breakdown
•
•
Common Base: Similar to single p-n junction VCB0 VBD(B-C)
Common Emitter: more complicated
1.
2.
3.
4.
5.
holes injected by FB emitter to base
holes generate e-p pairs in C-B depletion
e- drift back into base
e- injected to emitter
more holes into base…..
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Avalanche Breakdown: Common Emitter
IC dcIB ICB0
Mdc
ICB0
IB
1 Mdc
1 Mdc
• IC when M1/dc
• M only needs to be slightly greater than unity
• VCEO<VCB0 – Breakdown voltage is lower for common Emitter
mode than common Base mode or p-n breakdown voltage due
to amplification effect within the transistor
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Ideal
W/base width mod
Early Effect
W/base width mod
& avalanche
multiplication
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How can we mitigate these effects?
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Graded Base
•
•
•
•
Implant or diffusion leads
to doping profile
Doping profile leads to E
field
If Emitter is on top layer –
E field acts to push
carriers toward the
collector
Improved speed if limited
by base transport time
E
kT 1 dNB ( x )
q NB ( x ) dx
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Si-Ge HBT’s for BiCMOS
• Dilemma for bipolar transistors:
– For high frequency operation want low base resistance – high
base doping
– For high current gain want to minimize hole injection into
emitter (npn) – low base doping
• Solution HBT – heterojunction bipolar transistors
• For CMOS integration use Si1-x Gex system
–
–
–
–
Bandgap difference (1.12 eV Si, 1.0 eV, Si0.8Ge0.2)
80% EG in VB
0.1 eV additional barrier for holes to emitter
Higher base doping w/same gain
• Selective growth of pseudomorphic Ge on Si substrate
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Si-Ge HBT’s for BiCMOS
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Bandgaps and alignments
Si
Si0.8 Ge0.2
Ge
Vacuum level
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Si-Ge Heterostructure
Silicon:
Si0.8 Ge0.2 :
Ec
Eg
1.1eV
small = 20% of Eg
Eg
Ev
1eV
large = 80% of Eg
• Most of the bandgap difference shows up in the valence
band
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Band Diagram for SiGe HBT
electron
barrier
hole
barrier
Hole barrier is higher by ~ EV ~ 0.1 eV !!
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Si-Ge HBT’s
For EV ~ 0.1 eV, new exponential multiplier equals:
EV
~e
kT
e
0.1
0.0259
1
50
SiGe Heterojunction cuts backward hole injection by ~ 50:
Use higher gain if needed
If more gain not needed, increase BASE DOPING by 50
- Retain gain of previous pure Si transistor
- Reduce "base resistance"
=> more efficient operation
=> FASTER operation (reduced R-C charging time)
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Si-Ge HBT’s
dc = DBLENE /DEWNB
dc = DBLE(ni2/NB) /DEW(ni2/NE)
HBTdc = dc(nSii)2/(nGei) 2
= dc e(EGeG-ESiG)/2kT
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Gain Plots
VCE or frequency
On frequency versions can plot either:
Power gain
Current gain
=> rolls downward at frequency = " max
f "
=> rolls downward at frequency = " ft "
(Have seen designers ~ come to blows over which more important!)
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Gummel Plot
Log( I)
IC
Hermann-Gummel
IB
ratio =
VBE
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BJT Small Signal Response
• Assume the transistor can follow AC voltages and currents
quasistatically (frequency not too high). Also neglect
capacitances of pn junctions and other parasitics
Common Emitter equivalent circuit model
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BJT Small Signal Response
I B I B (VBE ,VCE )
I B (VBE v be ,VCE
I B
I B
v ce ) I B (VBE ,VCE )
v be
v ce
VBE V
VCE V
CE
BE
IC IC (VBE ,VCE )
IC (VBE v be ,VCE
IC
IC
v ce ) IC (VBE ,VCE )
v be
v ce
VBE V
VCE V
CE
BE
i b g11v be g12v ce
i c g 21v be g 22v ce
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BJT Transient Behavior
As with diodes, switching often limited by external circuit:
IC
IB
Rsource
Vsource
N
Rload
P
Vsupply
N
IE
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Right Circuit Loop:
IC
Tra
IC
Vsupply
Rload
"Load-line"
VCE
Vsupply
VCE
Transistor is constrained by load-line:
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Vsource
time
IC
time
build up Q steady-state
discharge discharge
limited by of remainder
ext. circuit
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