Transcript 020606 - HEP, Imperial

UK/HCAL common issues
Paul Dauncey
Imperial College
Outline:
• UK commitments
• Trigger issues
• DAQ issues
• Readout electronics issues
Many more questions than answers!
6 June 2002
UK/HCAL common issues
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UK commitments
The CALICE-UK groups have bid for funding
to do:
• Physics prototype ECAL readout electronics
– This might be reusable for tile HCAL but we are
short on engineering effort for major extra work
• Physics prototype general data acquisition
(DAQ) system
– This must include control of the trigger, but we
will not have funding for the trigger itself
We will hear if funded in ~ three weeks (1 July)
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Why am I at an HCAL meeting?
We are currently writing specifications for the UK items:
http://www.hep.ph.ic.ac.uk/~dauncey/lc/specification.ps
To complete this, we need to know:
• What are the HCAL interactions with the trigger?
• What are the HCAL interactions with the DAQ?
• Are there small changes we can make to the readout
electronics to enable it to work easily with the tile
HCAL?
The answers may already be known:
• If so, please direct us to the documentation!
• If not, can we make decisions soon?
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Trigger: latency
What is the allowable latency of the trigger?
• The ECAL needs the sample-and-hold to be
timed to coincide with the shaped pulse peak at
180ns after the event
• What are the corresponding numbers for the two
HCAL options?
– How sensitive is the timing?
– Where will the timing be adjusted?
– Will it vary channel-to-channel?
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Trigger: distribution
What inputs from the trigger are needed?
• Will trigger distribution to the whole of the
HCAL be done within its electronics?
– If not, how many input trigger lines are needed?
– What signal level will they be; LVDS?
• Will the HCAL allow a trigger to be aborted?
– Required in ECAL if second particle arrives within
~ 100ns
– Will HCAL electronics be retriggerable without
readout?
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Trigger: calibration
Is there HCAL front-end circuitry for a calibration signal?
• How will selection of this be done?
– Trigger must be switched to calibration mode
• Is timing identical for calibration and real events?
– ECAL may need different times to the sample-and-hold
between the calibration pulse and real events due to change
of pulse shape
– Is this true for the HCAL? If so, where will the adjustment be
made?
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DAQ: event sizes
What are the expected data sizes?
• ECAL will not be threshold-suppressed
– 9720 channels with 16 bits every event ~ 19 kBytes
• What are the corresponding numbers for the HCAL
options?
– ? Tile HCAL is up to 1200 channels, each 16 bits, so total ~ 2
kBytes
– ? Digital HCAL is up to 38 layers, 10k channels/layer, total
380k channels, each 1 bit ~ 50 kBytes
• Will the HCAL have threshold suppression?
– If so, what are the expected number of channels to read out?
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DAQ: event numbers
What are the requirements for numbers of events?
• What event rate is needed for the DAQ?
– We assume 100Hz is adequate, 1kHz is prefered
• What is the total number of events needed?
– We assume ~ 106 events per set-up (i.e. energy, particle
type, etc.)
– We assume between 10 and 100 set-ups (? e.g. what range
of energies are needed?) giving 107 to 108 events total
– Total sample of 108 events at 100Hz is 106 secs or 2 weeks
actual running time
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DAQ: electronics
What is the readout interface?
• ECAL will be purely VME
– Crate controller, trigger board and 15 readout
boards occupy 17 slots of 21 slot crate
• Can HCAL be made VME also?
– If so, then how many slots are needed? If HCAL
can fit into four slots, only one crate needed
– If not, a VME accessible interface (e.g. from
CAMAC) will need to be supplied
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DAQ: other issues
• What is the output data format?
– Needs to be machine-independent and easy to use
– We suggest ROOT-based files
• Are we restricted by a 2 Gbyte file size limit?
– Older operating systems will not deal with bigger
files
– Older ftp will not transfer bigger files
– With digital HCAL, this is only ~30k events, i.e. 5
minutes of running
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Readout electronics
Can ECAL readout boards be used for tile HCAL?
(We assume digital HCAL is too different…)
• Interface is through 36-pin connector
– 18 signals,
– Mixed analog and digitial
– All differential
• Not yet completely defined
– Still time for changes
• Each ECAL readout board handles 6 cables
– Identical signals on all 6
– Total of 15 boards, 90 cables in system
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Connector signals
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ECAL VFE
• ECAL Very Front End (VFE) chip handles 18
channels
– Serial readout using a shift register
– All shift register logic controlled by FPGA on readout
board; can be made flexible, e.g. number of clocks
– What is readout scheme for tile HCAL? Is it multiplexed?
Is it compatible with these connectors?
• Analog channel output digitised using (we hope!) 16bit ADCs
– Maybe 14-bit if cannot find fast enough components
– Voltage range not yet specified; what is range for tile
HCAL? Mounting different level converters would be
possible if we can find compatible components
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Conclusions
• Many unknowns (to us) which need to be
determined before we can finalise the
specifications
• Schedule for first readout board prototype is
early 2003
– Need ~ 6 months to design (from scratch)
– Need answers to questions within ~ 1 month
• We will try to retain maximum flexibility
– But difficult if significant cost or effort
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