Transcript p130_holman_poster

DC/DC Switching Power Converter with
Radiation Hardened Digital Control
Based on SRAM FPGAs
MAPLD
2004
F. Baronti 1, P.C. Adell 2, W.T. Holman 2, R.D. Schrimpf 2, L.W. Massengill 2, A.F. Witulski 2, M. Ceschia 3
1 University
2
of Pisa, Dept. Inf. Eng., Pisa, Italy
Vanderbilt University Institute for Space and Defense Electronics, Nashville, TN, USA
3 University of Padova, Dept. Inf. Eng., Padova, Italy
Introduction
Design of a digitally controlled boost converter
• DC/DC switching converters are essential
L
components for a satellite Power Control
Unit.
Digital control vs. analog control
 Increased flexibility, reduced sensitivity to
•
V
RL
1
controller
Vg
1 D
• Digital Pulse Width Modulator generates
the MOSFET switching signal
t
DT
SRAM-based
FPGA


COTS SRAM-FPGA implementation of the
digital controller
 Higher density, lower cost, and faster turn-
Deadzone
comparator
ADC
Vref +
+
• High-efficiency switching boost converter steps up an unregulated input voltage to a
regulated output voltage.
down
up
up = 0
down = 0
ADC and an SRAM-based FPGA to digitally
control the duty cycle D and regulate the
output over a wide range of input voltages and
load conditions.
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FPGA design
up/down
Counter
DPWM
V
Boost
Converter
H
• The feedback loop is implemented using an
around time compared to ASICs
 Reconfigurability (on-orbit design changes)
 High sensitivity to single event effects
C
H
noise, reduced sensitivity to component
parameter variations
More complex control algorithm
Easier to harden against radiation
•
Vg
T
• 1 bit resolution ADC (comparator)
• Up/down counter implements the digital
V
• Simple design, low power consumption
• The use of a deadzone comparator
avoids undesired oscillations
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Radiation hardening of the digital controller
 Configuration memory bit flip
 Low LETth= 0.1 - 0.5 MeV cm2/mg
 Full functionality recovered by
Single Event Functional Interrupt
(SEFI) is the dominant radiationinduced error in SRAM FPGAs:
•
reconfiguring the device
Recovery from an SEFI occurrence:
Error detection and correction logic
SEFI Detection:
 Each FPGA continuously monitors the status of the other

SEFI causes missing pulses in
the generated PWM control
signal of the converter
Dual redundant self-mitigating technique
FPGA1
Large transient drop at the
converter output
Error detection
and correction
logic
Logic
ENB
 Reload configuration bitstream
 Resynchronization of the two FPGAs. Two options can
Offline
1 Hi-Z
10
ENB
1 0
• SEFI Correction: two steps are necessary
01
/SEU ds
event
Logic
Use of a Radiation Hardness By
Design (RHBD) technique to
mitigate and correct SEFI
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FPGA
A SEFI occurrence is detected when an FPGA remains
in the Offline status for too long
be followed:
• Reset both devices (RHBD w/ reset)
 Disruption of current state for both devices results in
ds
Configuration
device
interruption of converter feedback loop.
 Undesirable transient pulse at the converter output
1
Logic
Error detection
and correction
logic
Dual redundant approach at
both logic design and device
levels
1
/SEU ds
event
Logic
1
1
1
ENB
FPGA2
results.
0
ENB
ds
• Reconfigured device loads current state from
The error
doesn’t
propagate to
the output
working device (RHBD w/ resync.)
 Converter output is not affected since working
device maintains the feedback loop.
 Requires additional logic to implement.
Results
Measured converter output
Test-bed architecture
VHDL simulation
FPGA1
recfg1
Reconfig.
emul. logic
17.98 ms
ENB
Logic
Error detection
and correction
logic
Logic
Error
inj.
pwm1
ENB
18.0 ms
28.0 ms
Conclusion
• Single event functional interrupts are the
28.02 ms
err. inj.
/SEU ds
event
ds
pwm1
•
pwm2
offline2
offline1
recfg2
Reconfig.
emul. logic
recfg2
ENB
Logic
offline2
/SEU ds
event
Error detection
and correction
logic
FPGA2
Logic
Error
inj.
ENB
ds
pwm2
offline1
• Recfg. emul. block forces
the FPGA output to hi-Z
status and initiates a reset at
the end of the
reconfiguration phase
• The error inj. block permits
simulation of an SEFI
occurrence in order to
validate design
recfg1
Recfg. phase
• SEFI injected on FPGA1
• FGGA1 output goes to Hi-Z state
• FPGA2 detects the invalid status of
FPGA1 and forces its reconfiguration
• After the reconfiguration and
•
Sync.
phase
synchronization phases, FPGA1
restarts operation with correct duty
cycle
• Very large output voltage
drop for the conventional
unhardened design
•
• Reduced (but unacceptable)
voltage drop for RHBD
w/reset design
•
• No voltage drop for RHBD
w/ resync. design
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3
dominant radiation error effect in SRAMbased FPGAs.
A SEFI-hardened DC/DC switching power
converter (boost topology) has successfully
been implemented using a reconfigurable
digital control loop based on FPGAs.
Dual redundant self-mitigation technique has
been applied to the converter to mitigate and
correct SEFIs.
An efficient approach has been applied to
resynchronize the two FPGAs after the
occurrence of a SEFI.
The design has successfully been validated
through VHDL simulation and experiments.
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