Transcript RF Transmitters

RF Transmitters
Architectures for Integration and
Multi-Standard Operation
Terry Yao
ECE 1352
Outline
Motivation
 Transmitter Architectures
 Current Trends in Integration
 State-of-the-Art Examples (3)

 Direct
Conversion
 2-Stage
Future Challenges
 References

Motivation
Increase in demand for low-cost, smallform-factor, low-power transceivers
 Proliferation of various wireless standards
pushes for multi-standard operation
 CMOS is well suited for high levels of
mixed signal radio integration [2]
 End goal: a low cost single chip radio
transceiver covering multiple RF standards

RF Transmitters
Function
Performance
Specification
Modulation
Accuracy
Frequency
Translation
Spectral
Emission
Power
Amplification
Output
Power Level
Transmitter Architectures

Mixer-Based
 Direct
Conversion (Homodyne)
 2-Stage Conversion (Heterodyne)
Both architectures can operate with constant and
non-constant envelope modulation
 Well-suited for multi-standard operation


PLL-Based
Show promise with respect to elimination of
discrete components
 Fundamentally limited to constant-envelope
modulation schemes  not suitable for multistandard operation

Transmitter Architectures

Direct Conversion
due to simplicity of the signal path  suitable
for high levels of integration
 Output carrier frequency = local oscillator (LO)
frequency
 Important drawback: LO disturbance by PA output
 Attractive
Transmitter Architectures

Direct Conversion – LO Pulling

Noisy output of PA corrupts
VCO spectrum -“injection
pulling” or “injection locking”

VCO frequency shifts toward
frequency of external stimulus

If injected noise frequency
close to oscillator natural
frequency, then LO output
eventually “locks” onto noise
frequency as noise level
increases
Transmitter Architectures

Direct Conversion – LO Frequency Offset Technique

LO pulling can be alleviated by moving the PA output
spectrum sufficiently far from the LO frequency

LO offset can be achieved by mixing 2 VCO outputs ω1 and
ω2 and filtering the result; leading to a carrier frequency of
ω1+ ω2, far from either ω1 or ω2

BPF1 must have high selectivity to suppress spurs of the
form mω1+mω2 to avoid degradation in quadrature
generation and spurs in the up-converted signal
Transmitter Architectures

2-Stage Up-Conversion





Another approach to solving the LO pulling problem
Up-convert in 2 stages so PA output spectrum is far from VCO
frequency
Quadrature modulation at IF (ω1), up-convert to ω1+ ω2 by
mixing and filtering
BPF1 suppresses the IF harmonics, while BPF2 removes the
unwanted sideband ω1- ω2
Advantages: no LO pulling; better I/Q matching (less
crosstalk between the 2 bit streams)
Current Trends in Integrated
Transceivers




Both direct and 2-stage architectures are used
(with modifications for better integration and
multi-standard operation)
Direct architecture  achieves a low-cost
solution with a high level of integration
[3],[4],[6],[8]
2-stage  results in better performance (ie.
reduced LO pulling) at the expense of increased
complexity and hence higher cost of
implementation [5],[7],[9],[10],[11]
Transmitter and receiver designed concurrently
to enable hardware and possibly power sharing
Direct Conversion Example

A 5-GHz CMOS transceiver frontend chipset [6]




Homodyne architecture
for better integration,
lower cost and lower
power consumption
Uses on-chip
quadrature VCO and
buffers to improve
frequency purity
On-chip VCO minimizes
radiation leakage from
strong PA output back
to core oscillator
Buffers isolate sensitive
VCO circuit from highpower, large voltage or
current swing circuit
blocks
2-Stage Conversion Example

A Dual Band (GSM 900-MHz/DCS1800 1.8GHz) CMOS Transmitter [7]



Exploits similarities of
GSM and DCS1800
standards (modulation,
channel spacing,
antenna duplexing) to
reduce hardware
2 quadrature
upconverters driven by
450MHz LO to generate
quadrature phases of IF
signal
IF signal routed to
single-sideband mixers
driven by a 1350MHz LO,
producing either 900MHz
or 1800MHz signal
2-Stage Conversion Example (#2)

1.75GHz Integrated Narrow-Band CMOS Transmitter with
Harmonic-Rejection Mixers [5]

Harmonic rejection mixer for
IF up-conversion relaxes onchip filtering requirements
and even eliminates discrete
IF filter  better integration!

HRM not only does
frequency translation, but
also attenuates the 3rd and
5th IF harmonics by
multiplying the baseband
signal by a 3-bit, amplitudequantized sinusoid
Future Challenges




Implementation of highly integrated radio
transceivers will remain as one of the greatest
challenges in IC technology
New architectures and circuit techniques should
be investigated for higher flexibility in CMOS
transmitters
Further improvement needed in the design of
on-chip inductors, filters and oscillators in a
standard CMOS process
Continued improvement in high frequency
CMOS device modeling and simulation
References
[1]. B. Razavi, “RF Transmitter Architectures and Circuits”, IEEE CICC, pp. 197-204, 1999.
[2]. A. Abidi, et. al., “The Future of CMOS Wireless Transceivers”, ISSCC, pp. 118-119, Feb. 1997.
[3]. J. Rudell, et. al., “Recent Developments in High Integration Multi-Standard CMOS Transceivers
for Personal Communication Systems”, IEEE 1998.
[4]. S. Kim, et. al., “A Single-Chip 2.4GHz Low-Power CMOS Receiver and Transmitter for WPAN
Applications”, IEEE 2003.
[5]. J. Weldon, et. al., “A 1.75-GHz Highly Integrated Narrow-Band CMOS Transmitter With HarmonicRejection Mixers”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, Dec. 2001.
[6]. T. Liu, et. al., “5-GHz CMOS Radio Transceiver Front-End Chipset”, IEEE Journal of Solid-State
Circuits, Vol. 35, No. 12, Dec. 2000.
[7]. B. Razavi, “A 900-MHz/1.8-GHz CMOS Transmitter for Dual-Band Applications”, IEEE Journal of
Solid-State Circuits, Vol. 34, No. 5, May 1999.
[8]. R. Point, et. al., “An RF CMOS Transmitter Integrating a Power Amplifier and a Transmit/Receive
Switch for 802.11b Wireless Local Area Network Applications”, IEEE RF IC Symposium, pp 431434, 2003.
[9]. S. Aggarwal, et. al., “A Highly Integrated Dual-Band Triple-Mode Transmit IC for CDMA2000
Applications”, IEEE BCTM 3.1, pp 57-60, 2002.
[10]. X. Li, et. al., “A CMOS 802.11b Wireless LAN Transceiver”, IEEE RF IC Symposium, pp. 41-44,
2003.
[11]. S. Mehta, et. al., “A CMOS Dual-Band Tri-Mode Chipset for IEEE 802.11a/b/g Wireless LAN”,
IEEE RF IC Symposium, pp 427-430, 2003.