Transcript Sisteme cu microprocesoare

Microprocessor-based
Systems
Course 9 Design of the input/output
interfaces (continue)
1
Transfer through direct memory access
(DMA- Direct memory access)
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Why is it used?
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Implementation mode:
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To increase the transfer speed
In order to release the main processor from the transfer task
Specialized circuit for handling the transfer – the DMA controller
The transfer is programmed by the processor and than it is performed
by the DMA controller: the transfer is made between the memory and
an I/O interface without the direct implication of the main processor
The transfer phases:
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Initialization: - the main processor programs the parameters of the
transfer (the DMA controller is behaving as a slave)
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The address of the memory zone
The direction of the transfer
The number of transferred data
The transfer phase: the controller performs the transfer and solve
the synchronization with the peripheral device (the DMA controller is a
master)
End of the transfer: the processor test the correctness of the
transfer by reading the status of the DMA controller (the DMA
controller is a slave)
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The scheme of connecting a DMA
controller into a microprocessor system
Memory
Address bus
Data Bus
μP
Command Bus
HOLD
HLDA
DMA
controller
DRQ
DACK
Input/Output
interface
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The sequence for handling a DMA request
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2.
3.
4.
5.
6.
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10.
11.
An interface requires a transfer by activating the DRQi signal to the DMA
controller
The DMA controller tests if the request is enabled and if there are no other
higher priority transfers in progress
If the request is enabled and there is no other request than it requests the
control of the bus by generating a HOLD signal to the processor
The processor finishes the last cycle on the bus and than disables its bus
amplifiers (leaving the control of the bus to the DMA controller) and grants
the HOLD request with the signal HOLDA (Hold Acknowledge) to the
controller
The DMA controller take over the control of the bus by activating its bus
amplifiers; it generates an address for the memory and DACKi (DMA
Acknowledge) signal to the interface
The DMA controller generates a memory read signal (MRDC/) or an
interface read signal (IORC/)
The addressed unit (memory or interface) generates the required data
The DMA controller generates an interface write signal (IOWC/) or a
memory write signal (MWTC/); as result the data is transferred from the
memory to the interface or vice-versa
The interface disable the DRQi signal and as a result the DMA controller
disables its bus amplifiers
The DMA controller disables the HOLD signal, giving up the control of the
bus in favor of the processor
The processor disables the HLDA signal, it activates its bus amplifiers and
continues with the execution of instructions
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Time diagram for a DMA transfer
Address
Data
CPU
CPU
DMA address
CPU addr.
DMA data
DRQ
HOLD
HLDA
DACK
MRD\
IOW\
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Internal structure of the I8237 DMA
controller
IOR\
IOW\
MRD\
MWT\
Decr.
Cmd.
block
CS\
AdrStb
AEN
RDY
CLK
EOP
DRQ0-3
DACK0-3
HOLD
HLDA
Base Base
addr. counter
Write reg
Inc./Decr.
Current Current
addr. counter
Addr.
Amp
A0-3
Adr.
amp
A4-7
Read reg
Data
amp
DMA
request
arbitration
Cmd reg
Status reg
Mask reg
Temp. reg
Request r
Mode reg
D0-7
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Features of the I8237 DMA controller
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can handle up to 4 peripheral devices (it has 4
independent DMA channels)
transfer speed 1,6Mocteţi/s
more controllers may be connected in a cascading
mode in order to increase the handled channels
the maximum dimension of a transferred block:
64KB
it can handle memory to memory transfers
More transfer modes:
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Single Transfer
Block Transfer (burst)
Auto-initialized Transfer
Memory to memory transfer
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Transfer through I/O processor
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When is it used:
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Implementation:
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a higher speed is required
the peripheral device is complex (it has a complex
behavior)
we want to discharge the main processor form I/O tasks
Input/Output processor +
Transfer program
we use DMA-like mechanisms and interrupts to
synchronize the main and the I/O processors
Types of processors used for this purpose:
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Specialized I/O processors
General purpose processors integrated into an interface
(ex: Z80)
Microcontrollers and signal processors (ex: 8048, 8032,
etc.)
Processors specialized for a specific peripheral device (e.g.
graphical processor)
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Advantages and drawbacks of the I/O
processor-based transfer
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Advantages:
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Higher speed
Can be adapted to the behavior of a
complex peripheral device (through a
program)
Drawbacks:
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Hard to implement and test
Higher costs
Concurrency problems on the system
bus and memory inconsistency
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Comparison between transfer modes
Transfer
Complexity
Cost
Speed
Processor
Involvement
Through
program
Small
Small
Small
total
Through
interrupts
Average
Average
Average
Significant
Through DMA
High
High
Small
Through I/O
processor
Very high
High
Very high High
Very small
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The serial interface
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Interface types:
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Serial transmission:
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Serial – reduced number of signals (2-3) and a bit-by-bit transfer
Parallel – a number of parallel signals (usually 8 for data and some for control);
transfer of data is made in parallel
A limited number of signals used for the transmission (usually 2 or 3 for a transmission
direction)
the transmission is made sequentially bit-by-bit
used for long distance transfers
used to interconnect a computer with a peripheral device or two or mode computers
Serial transmission types:
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Based on the synchronization mode:
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based on the interconnection mode:
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synchronous serial transmission – the transfer is controlled with a clock
signal
Asynchronous serial transmission – no clock signal is used
point-to-point – connection between two equipments
Multi-point – more equipments connected on the same link
based on the direction of the transfer:
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Unidirectional transfer – only one direction
Bidirectional transfer:
 Full duplex – 2 independent directions
 Half duplex – 2 directions, but alternatively
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Synchronous serial transfer
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Issue: synchronization between the transmitter and the
receiver; when is the optimal time for reading the next bit
Synchronous transfer = the speed of the transfer is controlled
with a clock signal
Examples:
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I2C – serial bus for microcontrollers
the keyboard interface of PCs
Advantages: easy implementation, reliable on short distances
Drawbacks: extra wire for clock signal, limited transmission
distances
ceas
dată
0
1
0
1
Synchronous serial transmssion
1
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Asynchronous serial transfer
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no clock signal is used; synchronization is made
through the specific structure of the transmitted data
Types:
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Character-based asynchronous transmission
Message-based asynchronous transmission
The communication rules established through a
standard protocol
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The protocol specifies:
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Codification of the binary information (e.g. voltage levels,
current levels, light impulses, etc.)
The communication environment (twisted or coaxial wires,
optical fibers, radio waves, etc.); topology
The structure of the transmitted data
The method used for synchronization
The method used of error detection
The method used for the flow control
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The RS232 (V24) standard
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RS232 the best known and most used serial asynchronous
transfer standard
Information coding: voltage levels
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“0” – (+3..+15V) ; usually 12V
“1” – (-3..-15V); usually -12V
Communication environment: electric wires (including phone
wires)
The structure of the transmitted data:
serial
signal
idle
5,6,7,8 data bits
Start 0
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idle
Parity
1,2 Stop bits
synchronization: through the first bit, stop bits and
frequencies: 300,600, 1200, 2400,… 19200 Bauds
Error detection: parity bit
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The RS232 (V24) standard
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The data-flow control:
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Hardware – through pairs of signals
 DSR-DTR – Dataset ready, Data Terminal
Ready
 RTS-CTS – Request to Send – Clear To Send
Software: through special ASCII codes
 XON-XOFF – Start/stop transmission
Transmission distance: max. 100 m
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The RS232 (V24) standard
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Long range transmission through MODEM and
phone networks
DTE
DCE
RS232
Phone network
calculator
DCE
RS232
MODEM
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Signals:
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Modulated analog signals
TXD – transmission
RXD – reception
GND – ground
DSR – Data Set Ready
DTR – Data Terminal ready
RTS – Request To send
CTS – Clear To sent
RI - ring
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The RS232 (V24) standard
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Transmission modes:
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One direction,
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2 wires/signals
Emiter
TXD
RXD
GND
DSR
DTR
CD
RTS
CTS
Receiver
TXD
RXD
GND
DSR
DTR
CD
RTS
CTS
Unidirecţional transfer
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Bidirectional with software
control of data flow (XON –
XOFF)
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3 wires/signals
Emiter
TXD
RXD
GND
DSR
DTR
CD
RTS
CTS
Receiver
TXD
RXD
GND
DSR
DTR
CD
RTS
CTS
Bidirecţional transfer , protocol XO/XOFF
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Bidirectional with hardware
control of data flow (DTRDSR or CTS-RST)
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5-7 wires/signals
Emiter
TXD
RXD
GND
DSR
DTR
CD
RTS
CTS
Receiver
TXD
RXD
GND
DSR
DTR
CD
RTS
CTS
-Bidirectional transfer, protocol DTR-DSR17
Universal Serial Asynchronous
Controller (USART) I8251
D0-7
RD\
WR\
C/D
CS\
RST
CLK
Data
amplifier
Control
block
Transmission reg
TXD
Transmission ctrl
TCLK
Reception reg.
RXD
Reception ctrl.
RCLK
MODEM ctrl
DTR\,DSR\
RTS\,CTS\
Internal structure of the I8251 serial controller
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Other serial transmission standards:
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RS485:
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Features:
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digital information coding through differential voltages
(not through voltage levels)
twisted pair of wires for bidirectional transmission
more devices connected on the same cable – multi-point
transmission
used as low level protocol for industrial networks (ex:
Profibus, CAN)
Advantages:
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longer transmission range (till 1 km)
higher noise immunity (because of twisted wires and
differential coding)
used mainly in industrial environments
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The RS485 standard
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Other serial transmission standards:
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HDLC/SDLC
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Preambul
Serial asynchronous transmission on messages
used for network transmission
More efficient than the character-based
transmission (useful data/total no. of bits ration is
better)
Very good error detection mechanism (CRC)
Synchronization through PLL (Phase Lock Loop)
The structure of the transmitted data:
message
Adrress Control
Useful Date
CRC
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