Transcript Document
Research Activities in Power Electronics at UCF Presentation at Princess Sumaya University for Technology Florida Power Electronics Center Orlando, Florida USA [email protected] Outline of topics • About Florida Power Electronics Center • Single-Stage PFC Converters • Low Voltage DC-DC converters • Inverters • Generalized Analysis of DC-DC Converters WELCOME TO FLORIDA Orlando Area Florida Power Electronics Center Dr.Issa Batarseh – Director Dr.Wenkai Wu – Asst Director Power Factor Correction (PFC) Circuits - NASA Soft-Switching DC-DC Converters - I-4 Florida Initiative Low voltage AC-DC and DC-DC Converters - NSF Dynamic Modeling and Control - NSF Electromagnetic Interference and Compatibility - NSF Inverter Application / Photovoltaic Cell – Industry & I-4 High Frequency AC DPS – NSF & I-4 Smart Electronic Load Maximum Power Point Tracking System Multidisciplinary Research Group Topologies and Converter System Dr. Issa Batarseh Magnetics Dr. Thomas Wu Power Devices Dr.J J Liou Modeling and Control Dr.Zhihua Qu Packaging Dr.Louis Chow FloridaPEC - Team Peter Kornetzky Shiguo Luo Joy Mazumdar Wenkai Wu Khalid Rustom Wei Gu Duy Bui Wei Hong Shailesh Anthony Jia Luo Songqrian Deng Christopher Iannello Abdelhalim M Alsharqawi Jaber A.Abu Qahouq Jay Vaidya Shilba Reedy FloridaPEC.engr.ucf.edu Power Conversion TV sets Medical equipment AC/DC converter power supply Telecommunication device, and other industrial equipment Computer AC Source ~ Converter DC Load Single-Stage PFC Converters Definition of Power Factor a il(t) + vl(t) _ PowerFactor ( PF ) Load Real Power( Average) Apparent Power a' For linear load: vl(t) il(t) PF I rms Vrms cos cos I rms Vrms For nonlinear load : PF vl(t) il(t) V rms I rms (1) cos I rms (1) I rms V rms I rms cos K d K PF K d K Kd I rms (1) K cos THD THD Kd --Distortion factor, where I rms I rms I n 1 rms ( n ) --Displacement factor 2 2 I rms I rms (1) I rms (1) 1 1 100 K d2 Special Case K cos 1 PF 1 THD 1 100 100 2 1 THD 1 100 2 Typical Line Current Waveform Without PFC vl(t) + il(t) vc(t) DC/ DC Voltage Regulator Line current is zero when vl(t) < vc(t). RL PF 0.67 THD >110% il(t) t vl(t) Current magnitue (% ) vc(t) 100 90 80 70 60 50 40 30 20 10 0 1 3 5 7 9 Harmonic number 11 13 15 PFC Approaches i) Passive PFC converter ii) Active two-stage PFC converter iii) Active single-stage PFC converter Three Basic PFC Approaches vline(t) + iline (t ) vline(t) + diode rectification with L,C filter + CB dc-dc regulator ac-dc converter with PFC RL V o _ Controller Controller Passive PFC converter vline(t) + iline(t) + CB dc-dc regulator ac-dc converter with both PFC and regulation + RL V o _ Controller Active single stage PFC converter o _ Controller Active two stage PFC converter iline(t) RL V Special Family-Single-stage PFC AC/DC Converter AC/DC converter with PFC iline(t) vline(t) + + RL V0 Cs Controller PFC stage and DC/DC stage share the same switch Single Loop Prior Art i(t) 1:n L1 L2 + v(t) S Cs C0 R Advantage Simple + V0 Least component count Disadvantage Inherent Low efficiency + Vc High DC Bus Voltage Stress (a) Boost/flyback combination DCM+DCM (Redl, 1994) i(t) + v(t) L1 Turn off spike 1:n Cs1 L2 S C0 Cs2 1:n (b) Boost/forward combination DCM+DCM (Russian circuit, 1992) R + V0 Advantage No turn off spike Low voltage rated capacitor Disadvantage Inherent Low efficiency High DC Bus Voltage Stress Conventional Energy transfer concept Ac input PFC cell eff. 1 Rough DC power 1 DC/DC cell eff. 2 Final DC output power 1 2 New energy transfer concept Direct transfer power (1-k)1 1-k Ac input PFC cell eff. 1 k DC power k1 DC/DC cell eff. 2 k12+(1-k) 1> 12 DC output power k12 +(1-k) 1 New Concept T1 Vin n1:1 |Vin| D3 L11 D1 L12 D2 D4 + + Vcs L21 L22 Vo - T2 S n2:1 • Flyboost PFC cell + Flyback DC/DC cell • Single active switch + single controller Operation mode |Vin| Flyback Mode Boost Mode Flyback Mode Boost Mode Flyback Mode Vcs - n1*Vo t tx T/4 T/2-tx T/2 T/2+tx T-tx • Flyback mode: |Vin| < Vcs – n1 * Vo • Boost mode: |Vin| > Vcs – n1 * Vo T Simulation results 40A 0A SEL>> -40A I(L1) 10A 0A -10A I(L2) 10A 0A -10A 10ms I(L3) 15ms 20ms 25ms Time Operation waveform in one line cycle Trace 1 Current through flyback winding Trace 2 Rectified input current Trace 3 DC/DC stage current 30ms Apply to other topologies T1 i1 (t ) v(t) 1 : n1 D1 Cs1 D5 L0 D3 VDS S D6 D2 D4 Cs 2 VCS T2 1 : n2 C0 R0 V0 Experimental Results a. Measured Power Factor vs. line voltage b. Measured Efficiency vs. line voltage c. Measured storage capacitor voltage (Vs) vs. line voltage d. Line voltage and line current at line voltage=110V AC. Trace A: Line voltage (100V/div, 5ms/div); Trace B: Line current (measured after auxiliary line filter;1A/div; 5ms/div). The measured Power Factor is 99.4% Special application Bi-Flyback Converter T1 i D1 D1 n1 : 1 T2 n2 : 1 Vin i2 i1 + Vin D3 L11 D1 C0 CS + L12 D2 D4 VO + + Vcs VDS - D2 iD 2 + S T1 n1:1 |Vin| VCS • Inegrate Bifred and Flyboost topologies • Two flyback transformers, single switch • Single DC bus capacitor L21 L22 Vo - T2 S n2:1 Soft switching application T1 n1 : 1 D1 T2 n2 : 1 Vin ia S2 D2 + ib L2 C0 VCC ic + S1 Flyback t1 C DS Flyback Boost T 2 t1 Cc T 2 Cs + VCS T t1 T Boost T 2 t1 Vin (t ) n1V0 Vcs n2V0 Vo - Developed prototype Waveforms Line Voltage Line Current Line Voltage Line Current Input voltage: 110V Output watts 150W Input voltage: 220V Output watts 150W Waveforms for the main switch Vds Id Efficiency and Power Factor 1 Power Factor 0.99 0.98 0.97 0.96 0.95 0.94 0.93 85 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 265 Input Voltage (V) 200KHz/[email protected] Improved Results 86 Efficiency (% ) 84 82 80 78 76 74 72 24.3 46.7 77.5 94.6 116 129 144 155 167 172 Output pow er (W) 178 184 191 199 200 Key Features • Higher efficiency due to soft switching operation of the main switch. • Low DC bus voltage make commercially available capacitor can be used as the energy storage part • Higher efficiency due to direct energy transfer in Flyback mode • Higher power density due to high frequency operation, which also benefit from soft switching Powering Future Generation of Microprocessors and ICs Low-Voltage High-Current Fast-Transient On-Board Voltage Regulator Modules (VRMs) Structure Internal DC bus Frontend AC/DC Isolated multi-output DC/DC Intermediate DC bus VRM#1 Fast load VRM#2 Load VRM#3 Load Load Load Off board AC Input AC-DC Converter DC-DC Converter Soft-Switching Single Stage PFC AC-DC Converter On board DC Bus Low-Voltage VRM Load The Main Power Supply Requirements (Challenges) 1. High output current slew rate (> 50A/s). 2. Low output voltage ripple and overshoot during transient (< 2% of the nominal output voltage). 3. High efficiency 4. High power density. 5. High VRM input current slew rate (<0.1A/s). 6. Packaging, thermal design, and EMC. Pentium 4 Voltage and Current Specs Current and Voltage Roadmap Year 1999 2000 2001 2002 2003 2004 2005 Vmax 1.8 1.8 1.5 1.5 1.5 1.2 1.2 Vmin 1.5 1.5 1.2 1.2 1.2 0.9 0.9 W 100 115 130 140 150 160 Imin(A) 50 56 77 87 93 125 133 Imax(A) 60 67 96 108 117 167 178 90 Lately, there are news about even lower voltages and higher currents expectations in the future (APEC’2001, March 2001) Interleaving Technique for Multi-phase Converters Single-Phase Inductor Current Single-Phase Ripple Driver 0 Phase-Shift Four-Phases Currents Phase I Vin PWM Vo Driver 360/N Phase-Shift Phase II Load Phase III Driver 2*(360/N) Phase-Shift Driver Lo ,eff Phase IV L o N Output Current of the Four Interleaved Phases 3*(360/N) Phase-Shift Four-Phase Ripple Four Times Frequency of a Single Phase Why Voltage-Mode Hysteretic Control and Interleave Technique? The Voltage-Mode Hysteretic Control The Interleave Technique Tracks the output voltage (ripple) and keeps it within the required limits. High frequency output voltage ripple with lower switching frequency Near instantaneous response to load transients. Ripple cancellation No feedback loop compensation is needed. No limitations on the switches conduction time Circuit simplicity + Current division between the phases Fast transient response which is limited by the feedback control loop Initial Experimental Prototype Waveforms Preliminary Results Phase 1 Drive Signal Phase 2 Drive Signal Phase 1 Inductor Current Input Voltage =12V Output Voltage =1.5V Output Current Phase 2 Inductor Current =30A Switching Frequency/Phase =400KHz Total Current Output Voltage Output Ripple Frequency =800KHz Initial Experimental Results Three-Phase VRM Control Two-Phase VRM Control Four-Phase VRM Control Transient Cancellation Control Method for Future Generation of Microprocessors The idea of the transient cancellation control scheme is to create a deliberate undershoot before an expected overshoot and vice versa to cancel the expected large overshoot to keep the output voltage within the allowable output voltage deviation limit. Ideal Output-Voltage Waveforms at High-to-Low Load Transient without the Transient Cancellation Controller Ideal Output-Voltage Waveforms at High-to-Low Load Transient with the Transient Cancellation Controller Future Look on VRMs and their Control Methods To satisfy future strict powering requirements of microprocessors especially the tight allowable voltage deviation (20mV), may have to be one or more of the following: 1) Proactive instead of reactive, i.e, to be able to take a response action before the load transients occur instead of after. 2) Future VRM controllers may need to be able to ‘learn’ the load behavior and/or apply advanced response techniques to reduce the VRM output voltage overshoots/undershoots and to have fast transient response. 3) Methods such as fuzzy logic and neural networks may be applied to make the VRM controller ‘smart’. 4) Advanced Topology techniques that have naturally the voltage deviation reduction (cancellation) Generalized Analysis of Soft-Switching DC-DC Converters Conventional DC-DC Converters (Hard-Switching) a Iin a S + Vin c isw IF Lo iD Vg + + + isw - D + Io Co vD Ro Vg Vo Vin Co Ro Vo S - - - VF iD IF c Lo S Lo isw Vg Vin b - Ci b D IF Vg + Li + - vD Co Lo Ro Vo Vin - + + c iD isw b Boost a a vD D Buck Iin - + b vD S D Co Ro - DS Vo + iD + c Buck-Boost Cuk a S Vin iD D + D + isw + vD Co Ro Vo Vin Lo S - Co Ro Vo - b c Zeta vD - Lo Ci Li Ci Li c isw iD + b a Sepic Switching-Cell Sharing a c a + - IF isw + c S iD Switching-Cell Vbc Vg=Vab Vg vD + D - IF + b - All the Conventional DC-DC Converters shares the same switching-cell With different orientation of the cell in a specific converter b The Conventional DC-DC Switching-Cell Analyzed Soft-Switching Cells a c isw + S IF iD Vg vD + D b (a) iLr vc r + Cr Lr vc r + Cr DS c iLr Lr S a + c - c a iD S Vg vD + vc r IF + iD D - DS Lr S VF IF vD + + Vg IF iLr Cr D - a + + CF iD Vg - D + vD - - b - b b (b) (c) + vc r (d) - Cr a + iLr S c Lr D1 D vD + vc r Cr DS a + c is w S Vg LT S1 - D1 - b is w S iD vD + D is w1 c a IF + Lr iT + Vg IF vD1 + iD Lr DS1 Vg - is w1 D1 b vD + D Cr S1 IF vD1 + b (e) (f) (g) (a) Conventional Cell, (b) ZVS-QRC Cell, (c) ZCS-QRC Cell, (d) ZVS-QSW CV Cell, (e) ZCS-QSW CC Cell, (f) ZVT-PWM Cell, and (g) ZCT-PWM Cell Zero-Voltage-Switching Quasi-Resonant S vcr + Cr - a Vg Vg+ZoIF vCr DS + D c iLr S Lr Vg IF iD vD + D iLr IF - t -IF b t0 ZVS-QRC Switching-Cell t1 t2 tc,on t3 t0+Ts ZVS-QRC Cell Basic Switching-Waveforms Zero-Voltage-Transition PWM S + vcr D S1 - D1 Cr Vg Vcr DS a + c iLr isw S Vg vD + D isw1 S1 D1 IF IF+(Vg/Zo) iD Lr - IF vD1 + b ZVT-PWM Switching-Cell IF isw VD -Vg IF iD t t0 t1 t2 t3 t4 t5 t6 t0+Ts ZCT-PWM Cell Basic Switching-Waveforms ZVT-PWM Family vcr + - Cr a Iin isw + c S Vg S1 is1 D1 Lo vD + Co Cr DS iD isw - c S - vD vD1+ Io + b D ZVT-PWM Boost vD + iD b + vcr IF Vin S1 Co Io Ci DS S S1 - Vin Lo b is1 Cr Ro Vo D1 Vg + Vg - a isw - vD1 + - Li Io D Lr is1 - c Iin + Vo - DS a Ro Co D1 - IF Cr Iin Vg Lr - ZVT-PWM Buck vcr S1 Ro Vo b + + S - Vin + is1 + vcr + vD1 + - Io iD D a isw IF Lr Vin Li Iin DS - L Ro iD D1 Lr + Co vD1+ D Vo + + vD - c ZCT-PWM Buck-Boost + vcr ZCT-PWM Cuk - Iin Li a Cr Iin DS a isw c S Vin D1 Ci + vcr Io Lo Vin Ci is1 Cr DS + Lo S1 S - + vD + D S1 IF iD Lr Li is1 Io isw vD1 + Co Ro Lr Vo - IF iD c Co D1 - vD D vD1+ + b b ZVT-PWM Zeta ZVT-PWM Sepic Ro Vo - The Generalized Transformation Table Vng I, nF Buck Boost Buck-Boost, Cuk, Zeta, and Sepic VnF I nT , , I nb Vnbc 1 M 1-M 1 -M 1-M 1+M 1 -M Single Generalized Transformation Table is complete and applies to all cells Generalized Gain Equation V Generalized gain ( Vnbc): ng Vbc Vsw V g 1 Ts Vg Ts v s (t )dt V g t0 t0 Ts (t2 t1 ) (t3 t2 ) Vg By using the normalized parameters: Vnbc f D ns d Vng 2 Summary of the Generalized Analysis (Basic Equations Intervals and Gain) CELL QV ng ZVS Quasi Resonant Converters ZCS Quasi Square Wave Vnf a Transition PWM QV ng MI nF M ( I nF I n , L1 ) Q Vng VnF ) ) I nT b I I cos 1 ( nf b nT MI nF QV ng ZVS sin1( Q VnF ) ng cos 1 ( ZCS CC MI nF (1 cos ) QV ng MI Vng Vnf a ) ) ZCS 2 VnF ng VnF cos 1 ( Q( Vng Vnx ) cos I nF I nT I nT N/A N/A N/A 2 f ns N/A N/A N/A V nx V ng M I nT sin ( I nF I nT ) Q f ns MI nF 2 Vng ( sin cos ) 2 2Q ) 2 f ns N/A N/A N/A N/A N/A N/A 2 f ns Q ( Vng VnF ) ( I nF I n ,L1 ) 2 M 2 Vnbc M IT 2 Q 2( ) MI nT 2 fns 2 D1 2 fns d M 2 ( I nF I n , L 0 ) 2 VnF Q f ns MI nF 2 MI nF Vng ( 1 cos ) Vng 2 2Q Q Vnbc I nb ) 2 f 1 MI nF QV ng 2 f ns QV ng D MI nF ( D D1 ) 1 D d 2 f ns b ( I nF I nT ) 2 ( D d N/A The time delay between turning OFF S1 Q Q V nF (V ng V nF ) sin I nF M M I n , L1 I nF and . fns (1 ) 2 2 Vnbc f D ns d Vng 2 N/A I n ,L0 Q (Vng Vnx )) 2 M S d Vn b c Vn g 2 (1 D1 D ) f ns Where: a ( GAIN EQUATION Vnbc 2 f ns ns (1 cos ) cos 1 ( V ( I nF I nT ) sin I nT sin1( MI ng ) nF MI nF QV ng cos1 ( QV MI nF cos 1 ( ZVS CV Q V nF sin ( I nF I n , Lo ) cos M Voltage Gain versus Duty Ratio Final Remarks • A generalized analysis method for well known families of soft-switching dc-dc converters was proposed. • It was shown that a single Generalized Transformation Table for all the converter families exists. • The simulation results verified the theoretical results. • The analysis generalization leads to several advantages such as: (1) Gives more insight into the converter-cell operation. (2) Improves the computer-aided analysis and design. (3) Simplifies mathematical modeling. (4) The cell-to-cell comparison becomes easier. (5) Improvement is made easier by deriving a new generalized cell. Functional Block Diagram READY SIGNAL VDC link 1 / f cont V p , cont V p , ref wt 1 / f ref v (t ) o 48VDC Vdc wt Vdc To PHASE A FUEL CELL DC-DC STAGE DC-AC STAGE LC FILTER EARTH PHASE B PROTECTION PWM CONTROL SPWM CONTROL Vref Vref Block Diagram of the power stage idc ac + vdc _ iac Push-Pull stage Inverter Stage DC-AC DC-DC Gate pulse PWM Vref Vcap Low -Pass Filter Gate pulse SPWM iL vo Vsin vac Design Specifications for 1.5kW prototype 1. 2. 3. 4. 5. 6. 7. Output power rating Output voltage Frequency Design input source type 1.5 kW continuous, Split single-phase 120 V/240 V nominal 60 Hz 0.1 Hz. Fuel cell, photovoltaic or other qualified renewable energy sources. Nominal rating of 48 V dc. Overall efficiency Higher than 90% for resistive load. Total harmonic distortion Output voltage THD: less than 5% when supplying a standard nonlinear test load Voltage Regulation +/- 6% from NL to FL. Frequency +/- 0.1 Hz Troubleshooting!!!!! Experimental Result (Output Voltage) 2001 Future Energy ChallengeTM :Competition funded by the U.S. Department of Energy and the Department of Defense to design and build, at one half or less of the cost of today’s equipment, a key low cost fuel cell component for converting direct current into alternating current in ten kilowatt or smaller fuel cells. Finalist： 1. 2. 3. 4. 5. 6. Texas A&M University Virginia Polytechnic Institute and State University University of Central Florida University of Wisconsin - Madison Drexel University University of Illinois, Chicago US DoE and DoD Improved sinusoidal output inverter topology solution: High Frequency Transformer DC High Frequency Inverter S1 Rectifier S3 T 1 Vd c SPWM Inverter L 1 S5 S7 C1 S2 S4 Complex Structure. High cost. Low Efficiency. L 2 C2 S6 Disadvantages AC LC Filter S8 L O A D Characteristics of the High Frequency Link Inverter No low frequency component exists in the waveform transmitted by transformer. A compact high frequency transformer is allowed for the transmission. The operation frequency of the two switches in the secondary side of the transformer is low. Thus leads to low switching loss and high efficiency. Low distortion of the output waveform. Simple structure, lower loss and higher efficiency can be obtained. Configuration of the proposed topology: S1 S3 T1 Vdc D1 D2 S5 L1 D4 S2 S4 D3 L O C1 A D S6 L2 Features No low frequency component exists in the waveform transmitted by transformer. A compact high frequency transformer is allowed for the transmission. The operation frequency of the two switches in the secondary side of the transformer is line frequency which leads to low switching loss and high efficiency. Low distortion of the output waveform. Simulation Circuit: We used half bridge in the primary side to illustrate the principle in the simulation. The whole system consists of power stage and control circuit. Simulation Result The Generation of the Modulating Signal: The modulating signal is generated by the comparison between the sampled signal and the reference wave. Comparison of the Two Inverter Topologies Inverter with Push-pull Structure 1. Complex system structure Novel High Frequency Link Inverter 1. Simple system structure DC-Sinusoidal AC DC-AC-DC-Sinusoidal AC 2. 3. 4. High voltage stress across the switches. All switches are operated at high frequency. High switching loss and low efficiency. Large size, high cost and difficult to design. 2. 3. 4. 5. Low voltage stress across the switches. Switches in the secondary side is operated at line frequency, switching loss drops greatly. Small size, low cost and easy to design. Low THD distortion at the output side. Dynamic Modeling of DC-DC Converters Dynamic Modeling (a) Detailed circuit model; predicting device behavior, time consuming , convergence. (b) Switched circuit model; Predicting roughly system large signal behavior, steadystate waveform and transient, details lost, time consuming convergence problems. (c) Equivalent PWM switch model; (1) Average switch model (Middlebrook) (2) Discrete time domain model (3) Three terminal PWM switch model (Vorperian) • • • • • Determination of steady-state operation point Optimization of the control loop Investigation of stability problems Prediction of large signal transient behavior Efficient computer simulation Special Problems to Model PFC Circuits Ac line input Switching power stage Output Control, d Feedback loop Digital modulator Error compensator No standard three-terminal network is available to single stage AC/DC converters, In most of cases, three terminals PWM model can not be used directly Using Circuit Analysis Technique while keeping Same functionality of each branch Derivation Sa L + vg(t) iL(t) L1 iL1(t) Cs2 vcs + vcs2 iD2(t) D2 S D1 Cs1 + vcs1 L2 1:1 C0 iL1(t) + v0 1:1 1:n iL2(t) 1:1:n ia2(t) ip2(t) vcs v0 / n L2 dTs D2 + v0 - L2 Da R iL2(t) d1Ts vcs v0 / n L2 Verification of the new model (DC) Output voltage (V) D=0.35 55 50 45 40 state-space averaging large-signal model 35 Storage capacitor voltage (V) 60 D=0.35 225 205 185 165 state-space averaging large-signal model 145 90 100 110 120 130 Input voltage (V) Output voltage vs. input voltage 140 90 100 110 120 130 Input voltage (V) Storage capacitor voltage vs. input voltage 140 Verification of the new model (small-signal) frequency response between line to output frequency response between control to output State-space averaging model vs. the new model (Vin: 110V, V0: 50V) Dynamic Modeling of DC/DC and PFC-AC/DC Converters PWM and Average techniques to derive closed loop transfer functions Explore New averaging method to equivalent average circuit Study decoupling circuit approach in non-three terminal converters