Transcript Wiring for CAN bus

Wiring for CAN bus
7 July 2015
Sébastien Franz PH-ATI-DC
Stéphane Detraz PH-ESS
ATLAS
DCS
1
CAN frame format
Arbitration occurs during the identifier field
and implies that multiple nodes simultaneously
drive their identifier bits onto the bus
7 July 2015
Sébastien Franz PH-ATI-DC
Stéphane Detraz PH-ESS
2
CAN bit segmentation
Sync_Seg
Fixed length, synchronization of bus input to
system clock
Prop_Seg
Compensates for physical delay times
Phase_Seg1
May be lengthened temporarily by synchronization
Phase_Seg2
May be shortened temporarily by synchronization
7 July 2015
Sébastien Franz PH-ATI-DC
Stéphane Detraz PH-ESS
3
Propagation delay
SOF bit
1st IDENTIFIER bit
The bit transmitted by node B must arrive at node A before the start of Seg1.
This condition defines the length of the Prop_Seg.
7 July 2015
Sébastien Franz PH-ATI-DC
Stéphane Detraz PH-ESS
4
Round-trip delay
7 July 2015
Sébastien Franz PH-ATI-DC
Stéphane Detraz PH-ESS
5
Round-trip delay
Tloop_trc: transceiver loop delay
 Tloop_cont: controller (+optocoupler) delay
 Tbus: bus propagation delay
Round trip delay = 2*(Tloop_trc+Tloop_controller+Tbus)

7 July 2015
Sébastien Franz PH-ATI-DC
Stéphane Detraz PH-ESS
6
Signal reflection

CAN signal noise margin
– Nominal bus levels according to ISO 11898
Dif. Voltage = 0V
But can be between
-500mV & +50mV
2V
7 July 2015
but can be between
1.5V & 3V
Sébastien Franz PH-ATI-DC
Stéphane Detraz PH-ESS
7