Transcript Document

Chapter 3: Noise Sources
Massoud Pedram
Dept. of EE
University of Southern California
Outline
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Background
Noise in Digital Systems
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Capacitive Crosstalk
Inductance Effects
Ground Bounce
IR Drop
Skin Effect
Electromigration
EMI
On and Off Chip Clock Frequencies
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Sources of Noise
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Noise in Digital Systems
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Noise
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Signals may be corrupted due
to many factors:
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Power supply noise
Crosstalk
Inter-symbol interference
Real noise (thermal and shot)
Parameter variation
Independent random variables
Power supply noise
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Inductance and resistance of
supply network cause voltage
drops
Spatial variation in the power
distribution network
Temporal variation in the
power supply voltage
Crosstalk
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One signal interfering with
another signal
Capacitive cross talk
between RC lines on a chip
 Floating
 Driven
Coupling between LC
transmission lines
 Near end
 Far end
Noise Sources
VN  KNVs  VNI
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The first component represents those noise sources that are proportional to signal
amplitude e.g., crosstalk and signal-induced power supply noise
The second component represents noise sources that are independent of signal
amplitude e.g., transmitter and receiver offsets and unrelated power supply noise
Proportional and Independent Noise
Sources
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Some of the noise sources
are proportional to signal
swing
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If you increase the signal
swing, you increase the noise
Crosstalk
Inter-symbol interference
Signal return ratio (Zr/Z0)
Signal-induced power supply
noise
Need to cancel these sources
of noise, not to overpower
them
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Some noise is independent
of the signal swing
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Receiver or transmitter
sensitivity
Receiver or Transmitter
offsets
Independent power supply
noise
Reference offsets
Power Supply Noise
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The power supply network
has parasitic elements
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Current draw across these
elements induces a noise
voltage
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On-chip : resistive
Off-chip: inductive
RI  L
Instantaneous current is
what matters
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Can be many times larger
than the DC current
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I
t
10W chip draws 4A at 2.5V
Peak current maybe 10-20A
High Speed Challenges
Signal quality of a single net: reflections and
distortions from impedance discontinuities in
the signal or return paths
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Crosstalk between multiple nets: with
ideal return paths
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Rail collapse in the power and ground
distribution network
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EMI from a component or the system
All signal integrity problems can be divided
into four categories. Each one has specific
causes. By identifying the causes of each
family of problems,design and technology
based solutions may be developed and
employed.
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Three Levels of Analysis
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Rules of thumb: Feed your intuition,
useful for order of magnitude estimation
First order approximations: Analytical
approximations, useful for quick estimates
and early design tradeoffs
Numerical simulations: Field solutions,
requires parasitic extraction, SPICE, or
IBIS simulations
Self inductance 
110nH/m
Don'ts and Do’s …
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Don’ts:
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Do’s:
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Base a final design on a rule of thumb estimate or even an
analytical approximation
Use rules of thumb and analytical approximations that are
inconsistent or lack fidelity
Automatically and immediately reach for a field solver in
every case
Know your rules of thumb
Know where to locate a range of analytical approximations,
each representing a non-dominated tradeoff point in terms of
accuracy and efficiency
Check rule of thumb, analytical expression and field
simulation for acceptable consistency and high fidelity
Use a field solver where and when absolute accuracy is
important
Maxwell’s Equations
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Capacitive Crosstalk
What Is Crosstalk
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Crosstalk is a disturbance caused by the electric or
magnetic fields of some signal affecting another
signal in an adjacent circuit
In an telephone circuit, crosstalk can result in your
hearing part of a voice conversation from another
circuit.
The phenomenon that causes crosstalk is called
electromagnetic interference (EMI). It can occur in
microcircuits within computers and audio equipment
as well as within network circuits
Capacitive Crosstalk to a Floating Line
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Capacitive coupling between
on-chip lines
Coupling over shared signal
returns
On-chip wires have significant
capacitance to adjacent wires
 On the same layer
 On adjacent layers
When two driven adjacent signals b
and c change, a voltage is induced
on a “floating” middle line a:
 Capacitive voltage divider:
 Signal is not restored
KC 
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Cc
Cc  Co
Va  KC (Vb  Vc)
K 2C 
2Cc
2Cc  Co
Capacitive Coupling to a Driven Line
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A simplified circuit model of two driven capacitively coupled lines.
Note that the aggressor makes an instantaneous transition (step
input). Vxtalk(t) gives the coupled voltage waveform on the victim line
2 and that line 2 is not changing itself.
Coupling to a Driven Line (Cont’d)
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If a victim line a is driven while an
aggressor line b changes, then a will be
disturbed but its steady state value will
be restored with a time constant of t =
R(Cc+Co)
If the signal rise time tr of line b is slow
compared to t, then the magnitude of
disturbance on line a will be reduced
The peak magnitude of voltage on line a
in response to a unit magnitude signal
on line b with rise time of tr is given by:
Cc
Cc  Co
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t

 tr

 t
1  exp   r
 t


 

Miller Effect and Wire Delays
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Capacitive crosstalk can affect the RC delay of signals
propagating down the line
If aggressor(s) switch in opposite direction of the victim, then
the effective capacitance is double the coupling capacitance
(due to the “Miller effect”) i.e., Ceff = 2Cc
If aggressor(s) switch in the same direction, the effective
capacitance becomes zero (capacitive crosstalk is eliminated)
i.e., Ceff=0
This can result in a large variation in the wire propagation
delay
It is also a major cause of timing noise (skew and jitter) in
VLSI circuits
Parallel Striplines
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0.18m CMOS technology
Devgan’s Metric
Aggressor
Ramp input
voltage source
Victim
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Devgan’s metric states that:
Vn  V par (n)  Rn
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tr , net ( j )
idesc(n)
jadj (i)
It determines an upper bound on the peak node voltage in the victim line in
terms of:
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
Cij
Coupling capacitance, Cij
Interconnect resistance (plus source resistance, if present) of the victim net, Rn
Rise time of at the output of the aggressor net driver, tr,net
Example Calculation of Devgan’s Metric
Agb
N2
Aga
N1
N0
Agc
N3
R2
N0
R1
N1
R3
R0=Rs
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N2
C1a
tr , net (a)
C3c
tr , net (c)
N3
C2b
tr , net (b)
Example of Devgan’s metric (cont’d)
R2
N0
R1
N1
R3
R0=Rs
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N2
C1a
tr , net (a)
N3
C3c
tr , net (c)
Noise voltage at nodes N1, N2, and N3 are:
 C
C2b
C3c 
1
a

V1  ( R1  R0 ) 


 tr , net (a) tr , net (b) tr , net (c) 


C2b
C3c
V2  V1  R2
;
V3  V1  R3
tr , net (b)
tr , net (c)
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C2b
tr , net (b)
Matrix Equations for Devgan’s Metric
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v1 is a vector of node voltages on the aggressor net
v2 is a vector of node voltages on the victim net
vs is the input to the aggressor net
Matrix Equations (Cont’d)
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Zeros in the conductance matrix indicate the fact that there is no
resistive path between net 1 and net 2
The zero in the voltage source coefficient vector is due to the fact that
the excitation is applied only to net 1 and net 2 is connected to ground
The matrix system can be rewritten in the Laplace domain as follows:
Note that the diagonal entries of capacitance matrices C1 and C2
correspond to coupling capacitances
Diagonal entries of the matrix Cc have a positive value
where
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Matrix Equations (Cont’d)
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Above equation may be solved by applying an excitation of B1k to the
aggressor net 1 while open-circuiting all capacitances connected to it
This implies that for an RC aggressor line with no path to ground, the
value of
at all nodes
Considering the circuit interpretation of
in
each
coupling capacitance can be replaced by a source of value k times the
coupling capacitance at the node; any capacitance to ground is removed.
Let us represent this vector of current sources be Ic
Then the equation would be
Then the value of V2,max can be obtained by solving net 2 with the above
transformation on all capacitances. This may be carried out by means of
a tree traversal
Pros/Cons of Devgan’s Metric
Vn  V par (n)  Rn

idesc(n)
jadj (i)
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CT Lij
tr , net ( j ) Sij
Lij is the length of adjacency between i and j , Sij is the separation
between the two, and CT is a proportionality constant determined by
the technology
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Advantages
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Disadvantages
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Convex and separable in Sij
The optimal spacing problem (OSP) becomes a convex and separable
mathematical program
No self capacitance or aggressor net resistance
Unbounded behavior for decreasing rise time and/or increasing coupling
length
Vittal’s Approach
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Gives a generalization of the Devgan’s metric
Accounts for the self capacitance and
resistance of the aggressor net
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No unbounded behavior
Replaces the “driver rise time of the aggressor net”
with an “effective rise time of the aggressor net as
seen by the victim net” as follows:
tr , net ( j ), net ( n) 
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tr , net ( j )
2
 Dnet ( j )  Dnet ( n)
Total Elmore delay for the aggressor net, Dj
Total Elmore delay for the victim net, Dn
Vittal’s Metric
Vn  V par (n)  Rn

idesc(n)
jadj (i)
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tr , net ( j ), net (n) Sij
The effective rise time of the aggressor net, net(j), as
seen by the victim net, net(n), is then a function of ALL
spacing variables. Therefore, it is
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CT Lij
Non-separable
Non-convex in general
OSP becomes very compute-intensive
Kuhlmann’s approach
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Waveform 1 shows the final value theorem method (Devgan’s metric)
Waveform 2 shows the real noise signal used in Kuhlmann’s approach
Kuhlmann’s approach (cont’d)
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Model the input voltage of the aggressor as an exponential function
where p corresponds to the time constant of the driver of the aggressor
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For computational efficiency, we use the following approximation for the
noise voltage induced on the victim net:
s
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Using AWE, the coefficients of V2(s) can be found according to following
equations:
Next we use V2(t) in the noise matrix equations which shows better results
than the Devgan’s metric
Capacitive Crosstalk Countermeasures
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Routing rules should be put in place to limit the
magnitude of the capacitive crosstalk between any
pair of signals
Floating signals should be avoided, and keeper
devices should be placed on dynamic signals to
reduce susceptibility to cross talk
Signal rise time should be made as long as possible,
subject to timing constraints, to minimize effect of
crosstalk on driven nodes
Sensitive signals should be separated from full swing
signals or even shielded by conductors on either side
that are tied to power or ground
Coupled Transmission Lines
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Circuit schematic of N onchip interconnects
Circuit schematic of N onchip interconnects that are
electromagnetically coupled
(may ignore the L values for
now)
Crosstalk between Transmission Lines
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A signal transition on one
transmission line induces forward
and reverse traveling waves on
adjacent transmission lines
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Consider the scenario:
dx
tx=dx/n
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Near-end crosstalk:
VC ( x, t )  krx VA ( x, t )  VA ( x, t  2t x ) 
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Far-end crosstalk:
VD ( x, t )  k fxt x
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VA ( x, t )
t
tx
Crosstalk (Cont’d)
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Inductive and capacitive
coupling add at the near end of
the line
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Inductive and capacitive
coupling subtract at the far end
of the line
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Both waves are positive
Pulse begins at beginning of
coupled section
In a homogeneous medium
cancellation is exact
Narrow pulse coincident with
wave on aggressor
Reverse and forward coupling coefficients:
k k
k k
krx  cx lx
k fx  cx lx
4
2
kcx 
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Cc
M
; klx 
Cc  Co
L
TX Line Crosstalk Countermeasures
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High swing signals should not be routed on
lines immediately adjacent to low swing or
other sensitive signals
The capacitive and inductive coupling
coefficients should be matched to eliminate
forward (far-end) crosstalk
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Place all signal lines between a pair of return
planes
If the forward coupling coefficient is nonzero,
avoid long parallel runs of transmission lines
When possible, both ends of all transmission
lines should be terminated in the characteristic
impedance of the line
Countermeasures (Cont’d)
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Signal rise times should be made as long as possible
subject to timing constraints
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Signals on adjacent layers should be routed in
perpendicular directions
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This reduces far-end crosstalk, which is directly proportional
to the signal derivative and this is reduced directly as the
derivative is reduced
Near-end crosstalk is proportional to the maximum difference
in the signal level across the coupled length and thus is
reduced proportionally once the rise time is greater than tx,
the coupled time
This results in zero inductive coupling and negligible
capacitance coupling
The two lines of a differential pair should be spaced
close together and far from the lines of other pairs to
keep the fields local to the pair
Inductance Effects
Introduction
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On-chip inductance effects have become increasingly significant
because:
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For performance considerations, some global signal and clock wires are
routed with large widths and thickness at the top levels of the metal to
minimize delays. This decreases the resistance of the wires, making their
inductive impedance comparable to the resistive part.
Z  R  jL
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Examples of Inductance effect
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As the clock frequency increases and the rise times decrease, electrical
signals comprise more and more high-frequency components, making the
inductance effects more significant.
With the increase of chip size, it is fairly typical hat many wires are long and
run in parallel, which increases the inductive cross talk and delay.
With the push of performance, some low-resistively metals,e.g. Cu wires,
have been explored to replace Al in order to minimize wire RC delays. This
could make the wire inductive reactance larger than the resistance.
Overshoot/undershoot edges
Ldi/dt voltage drop
Long range cross talk
Frequency dependent resistance
Adverse Effects of the Inductance
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Signal quality
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Ground bounce
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Distributed mutual inductance in uniform
transmission lines and lumped mutual inductance
(SSO)
Electromagnetic interference (EMI)
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Collapse of the power and ground rail voltage
Crosstalk
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Inductive discontinuity and ringing
Generation of common mode noise currents
Clock Frequency vs. Equivalent Inductance
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At 1 watt
power
dissipation, to
achieve 100
MHz clock
requires an
equivalent lead
inductance on
the order of
half a nH
What Affects the Magnetic Field Lines
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Magnetic field lines exist around
all current carrying conductors
The number of field lines depends on:
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Current in the wire
Proximity of the return path
Cross section of the wire
Other nearby currents
Material that the wire is composed of
Proximity of nearby metal surfaces
Dielectric material surrounding the wire
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The magnetic field line
density drops off with
distance
Types of Inductance
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Inductances may be classified as:
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Self inductance
Mutual inductance
Or they may be classified as:
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Partial Inductance
Loop inductance
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Loop self inductance
Loop Mutual inductance
Effective (or total) inductance
Self and Mutual Inductances
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Inductance is related to the number of field lines around the
conductor per ampere of current
Different types of inductance:
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Self or mutual
Loop or partial
Effective (total)
Self inductance
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# of field lines/amp of its own current
Mutual inductance
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# of field lines/amp of another line’s current
First-order Equation for Self Inductance
Radius=r
d
m0d   2  d
Lself 
 ln 
2   r
 3
  
 4
b
c
d
m0d   2  d 
1
Lself 
 ln 
  ln( )  
2   b  c 
2
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Note that  is obtained from lookup table. For more information visit:
http://home.san.rr.com/bushnell/self_inductance.htm
First-order Equation for Mutual Inductance
Radius=r
s
d
s
d
sd
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m d   2d
Lmutual  0 ln 
2   s
m d
Lmutual  0
2

  2d
ln 
  s
 

 
2
s  s  

 1  
 
d  2d  


Notice the change in mutual inductance with rod separation
Voltage Across the Inductance
I
V
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When the number of field lines around a conductor changes,
a voltage is induced:
N (LI )
I
dI
V

L
L
t
t
t
dt
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Partial Inductance
Inductance of
this part
Wire a
La
LM
Wire b (return path)
Lb
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Partial inductance is the portion of loop inductance for a
wire segment when its current returns via the infinity
Any loop can be divided into segments
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Every segment has a partial self inductance, which denotes the
number of field lines around the segment, when the only
current is through this section
Every segment has a partial mutual inductance to every other
segment, which denotes the number of field lines around both
segments, when current goes through only one section
Properties of Partial Inductance
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Partial self and mutual inductance are based on
geometry only
They may be obtained by using a 2D/3D field solver
such as Avanti’s Raphael or MIT’s FastHenry
The return path or the current loop may be
determined through spice simulations
The partial self and mutual inductances may be
frequency and proximity dependent
Loop Self Inductance
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The loop inductance accounts for the presence of the return
path current
Loop self inductance of coil b =
Total number of field lines around b
current in b
First-order Equation for Loop Self
Inductance
signal
Radius=r
s
Two parallel rods
return
d
m0 d s
Lloop, self 
ln( )

r
d
s
Two parallel planes
W
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s
Lloop, self  m0 d
w
Loop Mutual Inductance
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Loop self inductance of coil b = # of field lines per
ampere around b, which are due to the current in b
Loop mutual inductance of a and b = # of field lines per
ampere around a, which are due to the current in b
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First-order Equation for Loop Mutual
Inductance
a
b
h
Lloop, mutual 
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m0
2

a2b2
3/ 2
 a 2  h2 




For more information visit:
http://www.physics.uq.edu.au/people/ficek/ph348/sols/sol4/node4.html
Induced Voltages due to a Fixed dI/dt
D
dI a
self
Va, noise  Lself 
dt
R
a
a
b
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dIb
mutual
Va, noise  Lmutual 
dt
Effective Inductance

Effective (a.k.a. total or net) inductance is the total
number of field lines per ampere of current which are
around a section of a loop
Wire a
La
LM
Wire b (return path)
Lb
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
The effective inductance of wire “b” is:
Leff ,b  Lb  LM
Effective inductance
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Depends strongly on where the signal path is
Increases (decreases) if the return path is moved away from
(brought closer to) the signal path
Effective Loop Inductance
Wire a
La
LM
Wire b(return path)
Lb
Leff  Leff ,a  Leff ,b
 La  LM  Lb  LM  La  Lb  2LM


Loop inductance increases as wires are moved farther
from one another
Some key questions are:
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What happens to characteristic impedance as wires are moved
closer together?
What is the voltage drop across the whole loop for a fixed dI/dt?
What design features influence Lloop ?
Signal Risetime and Ringing Effect
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Inductance is the number of field lines per ampere of current
0.8mm wide or narrower wires do not have significant
inductance effects
The worst case inductance is when all aggressors switch in the
same direction
In general, with the inductance effect, signal rises faster. The
most serious inductance impact is high-Q ringing where
L/C
Q
R  Rs
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




Overshoot  exp 

 4Q2  1 


one-half 2 LC cause the
Rise times shorter than
worst ringing
The inductive cross talk noise tops off at lengths of around
4000m to 6000m length
Ground Bounce
Ground Bounce




Digital logic requires a stable, quiet, DC supply voltage while drawing a
large AC current with very high-frequency components comparable to
signal rise times (about 200A from power supply and derivative at the
point of use over 200GA/s)
The supply and ground are distributed over a network with inductive
and resistive components
The current causes IR drop across the resistive component
The derivative of current causes Ldi/dt across the inductive components
A Typical Power Supply Network
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The Power Distribution Problem

Modern digital systems operate at small DC voltages

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and draw large AC currents
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10A or more per chip, 100A per board, KA in a system
May go from 0 to full current in less than one clock cycle
over a supply network with parasitic elements
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M. Pedram
1.5 to 3.3V
must be held to within ±10% (or less)
Inductance of bus bars, PC boards, packages, and bond wires
Resistance of on-chip wires
Example of Ground Bounce Effect
A simplified circuit schematic of 16 output buffers switching
simultaneously
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Other Names for Ground Bounce
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Other names are:
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I noise
Switching noise
dI/dt noise
SSO (simultaneous switching output) noise
SSN (simultaneous switching noise)
A Typical Power Supply Network
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Actually a tree with branching at each level
Parasitic inductance (off-chip) and resistance (on-chip)
Power and ground networks are usually symmetric
Capacitance added to give a tapered frequency response
Typical Load Current
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For a given clock domain, load is usually periodic with the clock
May stop or start in a single cycle
With multiple clock domains, they may drift into phase
reinforcing one another
Load is often resistive, varying linearly with supply voltage
Some loads are high impedance, constant independent of supply
voltage
Local Loads and Signal Loads

Local loads pass current from a
point in the local power network
to one in the local ground network
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Signal loads connect a point in the
power network via a signal lead to
a distant point in the ground
network
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M. Pedram
Current can be supplied from a
nearby bypass capacitor
Usually due to unbalanced signaling
Current must return over a long path
Bypass capacitors are not effective
Inductive (Off-chip) Power Supply
Noise
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Each section of the supply network is an LC circuit
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Size the bypass capacitor to
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1/ 2
Has a resonant (natural) frequency,    LC 
LC

Inductor carries DC current (
LC)
Capacitor supplies AC current (  LC)
At LC, the LC impedance is infinite, thus, a small current
will cause large voltage oscillations
Supply cycle to cycle AC current with acceptable ripple
Handle inductor start/stop transient
Response of an LC Section to Typical
Supply Current

Over a clock
cycle,
inductor
current is
essentially
constant, Iavg ;
Load current
varies
considerably;
Capacitor
current is the
difference
between the
two;
Capacitor
voltage
ripples due to
this AC
current
M. Pedram
Bypass Capacitor to Handle Normal Load
in a Cycle
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Inductor carries the average (DC)
current and the bypass cap. supplies
the instantaneous (AC) current while
keeping supply variation less than
some threshold V
ki reflects the maximum fraction of
total charge transferred each cycle,
Qck, that must be supplied by the
capacitor at a given instant, t
ki  max
ki is a function of the waveform and
varies from a max of 1 for a delta
function to 0.25 for a triangle
waveform to 0 for a DC current Typical
value is 0.25 to 0.5
M. Pedram

t
( I  I avg )dt
0
tavg tck
Bypass Capacitor to Handle Start/Stop
Transient

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When circuit is off, inductor
current is 0
During startup, the capacitor
must supply current to the load
while the inductor current ramps
up
Similarly, when the circuit shuts
down, the capacitor must absorb
the inductor current while it
ramps down
In either case, the situation is
that of a step current into an LC
circuit
Response is a sine-wave
Vmax is the threshold for supply
variation
B
B
max
M. Pedram
Putting It Together: Sizing the Bypass
Capacitor

Bypass capacitor must be sized
to handle both types of inductive
power supply noise
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ripple due to non-uniform current
within a clock cycle
start/stop transients
maximum ripple can happen at peak
or trough of transient
Approximate capacitance
requirement by summing the
independent requirements
M. Pedram
i.e.
The Truth about Bypass Capacitors

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Most capacitors are only capacitors
at low frequencies
Capacitors have parasitic series
resistance and inductance
Every pico-farad has its very own
nano-Henry
Two key breakpoints
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LC frequency
RC frequency
Capacitors are ineffective at
bypassing currents above either of
these frequencies
Impedance vs. Frequency for Typical
Capacitors
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Controlling the Ground Bounce
Wire a
La
LM
Wire b(return path)
Lb
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Ground bounce
Vb  Leff ,b
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Minimizing the ground bounce:
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dIb
dI
 ( Lb  LM ) b
dt
dt
Minimize dI/dt: don’t use shared return path (instead use
multiple return paths)
Low Lb: use wide return path conductor (use planes, short
length)
High LM: put the signal close to its return path -- 50ohm signal
lines, low Z0 power/ground planes
Signal Path Topologies for Low Bounce

The following geometries have the lowest total
inductance of the current return paths:
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M. Pedram
Coaxial cable (which is not very practical)
Wide, closely spaced planes (too low a Z0)
Strip line
Micro strip
Twin lead
 Keep Zpower supply < 5% Zload
The golden rule in designing the power and ground
distribution network is to keep the impedance looking
into the power supply << Zload
Summary of Ground Bounce

Ground bounce
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Is the voltage drop across the return path
Can be caused by signal-returns or power-returns
Is minimized by controlling the total inductance of the return
path
Is strongly dependent on partial self inductance between
signal and return path
Is strongly dependent on partial mutual inductance between
signal and return paths
Primarily arises in packages and connectors
Anything (such as gaps in planes) that increases the total
inductance of the return path increases the ground bounce
Also drives common currents into the cables and creates EMI
IR Drop
Power Distribution Trends

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The on-chip power distribution problem is
getting much harder as technology evolves
Combination of
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lower voltages
higher current density
thinner metal layers
larger chips
We are quickly approaching the point where
peripheral bonding will not be adequate for
high-performance chips
Logic Current Profile
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Why does on-chip logic produce a ‘ spikey’ current profile?
Consider the logic that generates the current
Current is drawn to charge gate and wire capacitance Q=CV,
E=0.5 CV2
Typical behavior includes

circuit idle before clock edge

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exponential clock amplification just before clock edge

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exponential ramp up in current
Fan-in or selection in a logic circuit
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M. Pedram
current depends on activity factor
Fanout in a logic circuit

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exponential ramp up in current
flip-flops are clocked

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very little current
drop in current
Logic Current Profile Examples (Con’t)

A memory or register array
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A carry-lookahead adder
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M. Pedram
modest fan-out in PGK blocks
fan-out in carry tree
fan-in in carry tree, but with amplification
amplification to drive output
Control logic
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fanout in decoder
selection of word-line
amplification in S/A
selection in multiplexer
much like the decoder
fan-out in the first few stages
then tree fanning in to flip-flops
often a long, serial tail
Overall current profile is the superposition of all of these profiles
Worst-Case vs. Average Logic Current
Profile

Current drawn is often very data dependent
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For noise analysis we must consider worstcase power
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M. Pedram
e.g., a data path may switch 64-bits from all 0s to
all 1s
on average only 1/4 of the bits will have this
transition
when there is a transition at all
cannot allow possible, but unlikely events to cause
system failure
For battery life we may consider average
power
IR Drops

Power distribution network is designed to keep IR drop on VDD
and GND networks within limits

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Networks are usually designed specifically for the loads of a
given chip. However, we can gain insight into the process by
considering a uniform load
For example, suppose current densities are
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M. Pedram
– J peak = 0.3A/mm 2
– J avg = 0.05A/mm 2
For a peripheral bonded chip, VDD and GND are usually
distributed by combs with interdigitated fingers


e.g., for 10% supply variation, can drop at most 5% on each supply
– a hierarchy of such combs is often used
How much of a metal layer (or how many layers) do we need to
distribute this power?
Power Distribution Network: The Top-level
View
GND
VDD
M. Pedram
Calculation of the IR Drop
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A simplified equivalent circuit of one half of a pair of power buses is shown in
the above figure; Power and GND are supplied from the left side of the figure
The buses are then divided into N segments, each with resistance:
L p rw
Rp 
2 NW p
Lp is the total length of the global power buses; rw is the sheet resistance of
the wire, and Wp is the width of the global power buses
The current source associated with each segment supplies power to circuits
in an area of:
L pW p
Ap 
2N k p
kp is the fraction of the metal layer devoted to the power buses of one
polarity
IR Drop Calculation (Cont’d)

Voltage integrates along the strip, therefore, the IR drop from
the edge to the center of the two buses in a square shape chip
is:
N /2
N /2
2
VIR 

i J pk Ap R p 
i 1
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i 1
4N 2k p
Jpk is the peak current density
If N goes to infinity, the above equation can be written as:
VIR 

Lp / 2 J
0
M. Pedram

i J pk L p rw
J pk rw L p2
pk rw x
dx 
kp
8k p
IR Drop Countermeasures
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Use an area-bonded chip so that power
need not be distributed from the chip edge
Use more or thicker metal layers to
distribute the power to reduce the
effective resistivity, rw
Use on-chip bypass capacitors to flatten
the current profile so the distribution need
only be sized for average rather than the
peak current
Skin Effect
Transmission Line Loss Models
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M. Pedram
Losses that remain constant with
frequency can be modeled as:
 Dielectric constant
 Dissipation factor, tan(d)
 RDC
Other losses, RAC, are proportional to
frequency  f
Signal Propagation in the Frequency
Domain
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M. Pedram
When a sine wave is launched into a transmission line, the frequency of
the sine wave propagates unchanged, but the amplitude will drop off. As
it propagates, the amplitude will be exponentially attenuated. This can
be described with an attenuation per length coefficient, with the units of
dB per inch, for example
Modeling Lossy Lines in the
Frequency Domain
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M. Pedram
In general, we will be assuming that R and G may be frequency
dependent, but C and L will be constant in frequency, and will
use the high frequency limits for these terms. As we shall see,
frequency dependence of inductance can be accounted for in the
resistance term
Low Loss Approximation

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At low frequencies (towards the DC end), current is uniformly
distributed over the cross section of each conductor. We will refer to
these frequencies as the low-frequency region
As the frequency increases, due to the induced electric field, the
current distribution starts changing. There are three reasons :

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
Edge effect: the current tends to concentrate at the sharp edges of a
conductor which affects both the signal conductor and the ground
conductor
Proximity effect: particularly pronounced on the ground conductor, the
current of which tends to concentrate below the signal conductor as the
frequency increases
Skin effect: pronounced in the high-frequency region on both conductors,
where the current becomes concentrated in the thin layer at the surface
Microstrip
M. Pedram
Stripline
Skin Effect


The tendency of alternating current to flow near the surface of a
conductor, thereby restricting the current to a small part of the
total cross-sectional area and increasing the resistance to the flow
of current
High frequency current flows primarily on the surface of a
conductor with current density falling off exponentially with
depth into the conductor:
 d
J  exp   
 d 

The skin depth, d, the depth where the current has fallen off to
exp(-1) of its normal value is given by:
d   f m 

1/ is the conductivity of the material, and f is the frequency of
the signal
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1/ 2
The Origin of Skin Depth
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M. Pedram
At DC, if each ring has the same current, which one has more
inductance?
At high frequency, which ring has more impedance?
If you were an electron, where would you want to be?
The center path has the highest inductance since it has all the field lines
of the outer ring plus the field lines that are between it and the outer
ring. In general, the self inductance of the current path will decrease as
you approach the outer edge
Skin Depth Limited Current Distributions
M. Pedram
A Simple Approximation
Assume the signal path width is w and its thickness is t
M. Pedram
Resistance Modeling
Recall that f is in MHz
M. Pedram
Inductance is Frequency Dependent
M. Pedram
Electromigration and
Electromagnetic Interface
Electromigration
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Over long distances, current density must be kept low to avoid large IR
drops; Over short distances, current density must still be kept low to
avoid metal migration
Over time, wires that carry high current densities will fail as the metal is
eroded away

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think of your wire as a fuse
Migration threshold varies depending on process, temperature, and
lifetime
If a metal layer is subjected to an average current density of greater
than about 1mA/mm2 (109 A/m2), the layer will slowly fail
This is often a factor on short power buses that connect from the main
bus to a point of high current use
To avoid metal migration the fraction kp of metal devoted to each
power bus must satisfy:
3
kp 
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M. Pedram
10 J aw Lp
2t
where t is the thickness of the metal layer, Jaw is in A/mm2
It can also be a factor on the output of high-current drivers
Migration applies to vias as well as wires
Electromagnetic Interference (EMI)
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M. Pedram
Large external electric and magnetic fields can couple into circuit nodes
and cause noise
For both types of fields, susceptibility is reduced by keeping a minimum
distance between a signal and its return
For E fields, the induced voltage is proportional to the distance between
the signal and return path
For B fields , the amount of flux coupled is proportional to the area of
the loop between the signal and the return path
Electromagnetic Interference is rarely a problem in digital circuits unless
they are operated near large sources of fields
Usually, the larger concern is the interference created by the digital
system
The same techniques that reduce susceptibility to external fields also
reduce emissions by the digital system
Most digital systems can be made “quiet” naturally by keeping signals
and return paths close together, balancing currents in external cables,
controlling rise time on signals, and properly terminating lines
Appendix: How to Minimize Inductance
Effects

Dedicated ground wires
Lloop  L11  L12  L21  L22

Differential signals
Common mode noises such as inductive effects may be rejected
However, the design suffers from longer delays to Miller effect
M. Pedram
How to Minimize Inductance Effects
(Cont’d)


Buffer Insertion
Splitting wires
G
G
S
M. Pedram
S
Rl
L
C
, l , l
n kn / 2 n
S
S
G
S
S
G
G
S
G
S
S
S
; k 1
S
S
S
G
S
S
G
How to Minimize Inductance Effects
(Cont’d)

Termination
Shunt-RC termination
Series_R Shunt-C termination
Series_R termination
Diode termination

Continuous power/ground planes

M. Pedram
Continuous power/ground planes on-chip provides an impedancecontrolled low-loss signal lines
Appendix II:
Values for Single Supply Noise vs. Distance
M. Pedram
On-chip Parasitic Capacitance
M. Pedram
Typical Transmission Line Parameters
and Coupling Coefficients
M. Pedram