Transcript Link to Poster

A Reconfigurable and Programmable
Gigabit Network Interface Card
Jeff Shafer, Hyong-Youb Kim, Paul Willmann, Dr. Scott Rixner
Rice Computer Architecture: http://www.cs.rice.edu/CS/Architecture
Abstract
Hardware Design
Software Design
 In this project, we are designing and implementing a gigabit
NIC on a FPGA. This NIC will support research in network
server operating systems and network architecture design
 Why are existing NICs insufficient for this research?
 Current software programmable NICs (e.g. Alteon
Tigon) are too slow for modern complex offloading tasks
 Current ASIC-based NICs have limited functionality and
leave most tasks to the host processor. This architecture
does not scale well to high data rates
 Commercial products often use locked or proprietary IP,
limiting our design flexibility
 Why do we need a FPGA-based NIC?
 FPGA provides maximum flexibility for future research
 For architecture research, we need a flexible NIC with
hardware acceleration. This NIC is both reconfigurable
(runs frequent / demanding tasks in hardware) and
programmable (runs infrequent / flexible tasks in
software)
 Virtex-II Pro FPGA
 2 400 MHz PowerPC processors
 MAC controller - Complete
 DDR memory controller – Complete
 128MB - 1GB DDR Memory
 Serial Port Debug – Complete
 DMA engine – Pending
 Checksum Offloading - Pending
 Spartan-IIE FPGA
 64-bit/66-MHz PCI interface –
Complete
 2MB SRAM - Complete
 Event notification - Complete
 PowerPC processor runs custom
packet-handling firmware
 Interfaces with MAC controller
to send/receive packets
 Interfaces with DDR controller
to store bulk frame data
 Interfaces with DMA controller
to transfer data to/from host
 Interfaces with SRAM over
Spartan bridge to access PCI
control registers
 Custom device drivers written for
Linux and FreeBSD
System Architecture
PCI / FPGA Development Board
Ethernet
DDR-SDRAM
(256 MB)
Development Platform
Memory / Control
DDR Controller
PCI
Debug
PLB – 64b / 100 MHz
PLB / OPB Bridge
BRAM Block
Serial Port
Serial Port
DDR
Virtex FPGA
Spartan FPGA
Custom FPGA
Design
RJ-45 Port
Full Duplex
Ethernet
2 GBits/sec
RS-232
(Debug)
Ethernet PHY
(10/100/1000)
UART (OPB Bus)
MAC
Control
Spartan
Bridge
On-Chip Mem
PowerPC
300MHz
32b / 125 MHz
BRAM Block
8b / 125 MHz
32b / 66 MHz
64b / 66 MHz
Ethernet PHY
PCI Interface
PCI Bridge
SRAM
(2MB)
32b /
66 MHz
PROM
(Spartan FPGA)
OS Research
 Connection Handoff to NIC
 Offload network stack processing to NIC
 Reconfigurable NIC allows exploration of hardware /
software mechanisms to accelerate offloading process
 Thread Parallelization of Network Stack
 Parallel network stacks achieve high network throughput
but have synchronization challenges
 Control-synchronous parallel stacks use the OS
scheduler to ensure connections are always managed
by the same thread, eliminating some (but not all) locks
 Exploring ways to use NIC to eliminate device queue
lock to enable simultaneous communication among
multiple threads in parallel stacks
PCI Bus (64b / 66 MHz)
Hardware Research
Device Utilization
 What NIC architectures scale to support
future high-performance offloading at
multi-gigabit data rates?
 Can reconfiguring the FPGA hardware
provide a substantial performance
improvement for different applications? Is
this improvement greater than simply
upgrading the NIC firmware?
 Substantial headroom for future
development
Component
Utilization
Slice Registers
4 input LUTs (Logic)
8,257/ 27,392
8,357/ 27,392
30%
30%
BRAMs
Occupied Slices
Global Clocks
Digital Clock Managers
Total Gate Count:
100 / 136
8,573 / 13,696
13 / 16
5/8
6,890,605
73%
62%
81%
62%