投影片 1 - National Sun Yat

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Transcript 投影片 1 - National Sun Yat

Presenter: Min Yu,Lo
Kumar, S.; Jantsch, A.; Soininen, J.-P.; Forsell, M.; Millberg, M.; Oberg, J.;
Tiensyrja, K.; Hemani, A.
VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on
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We propose a packet switched platform for single chip systems
which scales well to an arbitrary number of processor like resources. The
platform, which we call Network-on-Chip (NOC), includes both the
architecture and the design methodology.
The NOC architecture is a m × n mesh of switches and resources are
placed on the slots formed by the switches. We assume a direct layout of the
2-D mesh of switches and resources providing physical- architectural level
design integration. Each switch is connected to one resource and four
neighboring switches, and each resource is connected to one switch.
A resource can be a processor core, memory, an FPGA, a custom
hardware block or any other intellectual property (IP) block, which fits into
the available slot and complies with the interface of the NOC. The NOC
architecture essentially is the on chip communication infrastructure
comprising the physical layer, the data link layer and the network layer of the
OSI protocol stack.
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We define the concept of a region, which occupies an area of any
number of resources and switches. This concept allows the NOC to
accommodate large resources such as large memory banks, FPGA areas, or
special purpose computation resources such as high performance multiprocessors.
The NOC design methodology consists of two phases. In the first
phase a concrete architecture is derived from the general NOC template.
The concrete architecture defines the number of switches and shape of the
network, the kind and shape of regions and the number and kind of
resources. The second phase maps the application onto the concrete
architecture to form a concrete product.
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 Single processors will not be able to utilize the
transistors of an entire chip. Single synchronous clock
regions will span only a small fraction of the chip area
 Applications
will be modeled as a large number of
communicating tasks. The different tasks may have very
different characteristics and origins. This will make a
heterogeneous implementation with different kind of
resources for different tasks the most cost effective
solution.
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IP-Centric
Methodology and
Design with the
SpecC Language
[5]
IP interface design and
system verification
Platform Tuning for
Embedded Systems
Design
[6]
Communication
infrastructure
[11,8,9]
Propose reuse system architecture
platform design methodology
On chip communication
reference OSI
[12,10,13]
Network on chip
Globally Asynchronous
Locallly Synchronous
[16]
System Level Design:
Orthogonolization of
Concerns and
Platform-Based
Design
[7]
Communication centric
Plarform developed
[8,9,10]
architectural,platform
and methodologies
System Level Design
This Paper
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 Network on Chip(NOC) architecture
◦ Develop communication infrastructure
 Backbone-Platform-System
Methodology
◦ Platform development
◦ Application mapping
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 Proposed CLICHÉ NOC architecture
◦ RNI(Resource Network Interface)
◦ Switch
◦ Resource
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 Switch component
◦ Each switch is connected to four other neighboring switches
through input and output channels.
◦ A switch consisting of mux,queue…
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 Resource component
◦ The resource can be a combination of all previous types.
◦ Since the area of resource equals one synchronous clock domain.
 RNI component
◦
◦
◦
◦
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Physical layer
Data-link layer
Network layer
Transport layer
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 The idea with the BPS is to encapsulate the design work
into reusable platform
 BPS has two main phases :
◦ Platform development
◦ Application mapping
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 Backbone design
 Platform design
 System design
 Methods and tools
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 Used a homogeneous 5 x 5 NOC architecture for our
simulation experiments.
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(1) 2-D Torus architecture
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(2) Folded Torus architecture
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 Conclusions
◦ The NOC concept has been necessitated by three factors:
 First there is the increasing demand of on-chip interconnect
bandwidth.
 The second equally crucial factor is to amortize the enormous
engineering cost involved in designing such large chips over multiple
applications.
 The third factor is demand for easy-to-use methods to exploit the
parallel processing capacity provided by multiple computational
resources.
 My Comments
◦ This paper proposed NOC design methodology, I multicore
interconnection study for the future is helpful.
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