Class 11.1 Jump Instruction.pptx
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Transcript Class 11.1 Jump Instruction.pptx
Jump and Branch Instructions
• Jump instruction.
• Symbolic address.
• Conditional Branches.
Textbook P&H: Chapter 3.5.Instructions for making
decisions.
Central Connecticut State University, MIPS Tutorial.
Chapters 17,18.
Repeat and Alter actions
The power of computers is:
their ability to repeat actions
and their ability to alter their operation depending on
data.
Modern programming languages express these abilities
using control structures.
Repeated action (iteration) is done with a while
structure.
Altered operation (alteration) is done with an if-thenelse structure.
Assembly builds the structures
The machine instructions of the processor mainly do
not have Repeat and Alter structures (Intel has
loops).
Consequentially Assembly language does not have
these structures.
When you program in assembly language you must
build these structures out of basic assembly
instructions.
These basic instructions are the jump instructions
and the conditional branch instructions.
What does Jump
[0x0040000c]
[0x00400010]
...
[0x00400020]
Control Flow
jump 0x0040 0020
other instructions
...
ori $8, $0, 4
Program Counter
0x0040 0004
Control Point
0x0040 0000
The effect of a jump instruction is to put a new address into the PC.
Now the next machine cycle fetches the instruction at the new address.
Instead of executing the instruction that follows the jump instruction in
memory, the processor "jumps" to an instruction somewhere else in
memory.
Jump syntax
j
target
main:
# after a delay of one
# machine cycle,
# processor jumps to target
sll
$0,$0,0
sll
$0,$0,0
sll
$0,$0,0
sll
$0,$0,0
j
main
addiu $8,$8,1 Branch delay slot
$8=$8+1
• This is endless loop.
• Is there anything changed in this loop ?
Jump Machine Instruction
[0x00400000]
[0x00400004]
[0x00400008]
[0x0040000c]
[0x00400010]
[0x00400014]
0x00000000
0x00000000
0x00000000
0x00000000
0x08100000
0x25080001
nop
nop
nop
nop
j 0x00400000 [main]
addiu $8, $8, 1
; 8:
; 9:
;10:
;11:
;12:
;13:
sll
sll
sll
sll
j
addiu
$0,$0,0
$0,$0,0
$0,$0,0
$0,$0,0
main
$8,$8,1
The intent of the jump instruction is to put the address
0x00400000 into the PC.
However, PC changes only after the instruction in the branch
delay slot has executed.
How does a 32-bit instruction specify a 32-bit address?
What does mean this machine code 0x08100000 ?
How the assembler forms it ?
How the computer translates that instruction back into the
address ?
Addressing Modes
5. Jump uses the
Pseudodirect addressing
mode, where the jump
address is the 26 bits of
the instruction
concatenated with the
upper bits of the PC
Addressing mode – One
of several addressing
regimes delimited by
their varied use of
operands and or
addresses.
Jump instruction format
Some of the instruction's bits must be used for the opcode.
There is room in the instruction for a 26-bit address.
The 32-bit target address is transformed by compiler
into a 26-bit address and is written into the instruction.
During execution the 26-bit target address field is
transformed back into a 32-bit jumping address by
computer.
How this is done ?
6
26
000010 00000000000000000000000000
opcode
target
26 bits keep instruction number (not
byte’s address)
[0x00400000]
[0x00400004]
[0x00400008]
[0x0040000c]
[0x00400010]
[0x00400014]
0x00000000
0x00000000
0x00000000
0x00000000
0x08100000
0x25080001
nop
nop
nop
nop
j 0x00400000 [main]
addiu $8, $8, 1
Instructions always start on an address that is a multiple of
four (they are word-aligned).
So the low order two bits of a 32-bit instruction address are
always "00".
6
26
27,28
0-0000
4-0100
000010 00000000000000000000000000 00
8-1000
C-1100
No need to keep the last 2 zeros in 26 bits of instruction.
They could be restored later during jump time
We have 28 bits. What with the 4 remaining
bits to have a full absolute address ?
We cannot do “jump to absolute address”.
Because we cannot keep more than 28 bits of address in
the jump instruction
But if we have some base address
then we can construct the full absolute address and
jump by that address.
That base is the PC’s high order 4 bits.
6
26
27,28
000010 00000000000000000000000000
00
PC
0000 0000 0100 0000 0000 0000 0000 0000
How is formed the absolute address
Shifting the 26-bit target left two places results in a
28-bit word-aligned address.
Now the high-order four bits in the PC are
concatenated to the high-order end of the 28-bit
address to form a 32-bit address.
Relative addressing causes the jumps to
be local
A jump instruction can't jump to any arbitrary location
in the full 32-bit address space
It must jump to an address within the following range:
wxyz 0000 0000 0000 0000 0000 0000 0000
.
.
wxyz 1111 1111 1111 1111 1111 1111 1100
The program is compact and mainly the most jumps and
branches are to nearby addresses.
If no other memory allocation technique (paging,
relocation, segmentations) is being used then OS should
place the program in the WXYZ segment in the way that the
program’s start and the end remain in that segment
Jump Example
Address
Machine Instruction
Assembly Instruction
00400000
0000 0000 0000 0000 0000 0000 0000 0000
sll $0,$0,0
00400004
0000 0000 0000 0000 0000 0000 0000 0000
sll $0,$0,0
00400008
0000 0000 0000 0000 0000 0000 0000 0000
sll $0,$0,0
0040000C
0000 0000 0000 0000 0000 0000 0000 0000
sll $0,$0,0
00400010
000010 00 0001 0000 0000 0000 0000 0000
j firstInstruction
00400014
0000 0000 0000 0000 0000 0000 0000 0000
sll $0,$0,0
1.
2.
3.
4.
5.
6.
Full 32-bit jump address:
0x00400000
The 26-bit field of the
jump instruction:
Shift it left two
positions:
What are the high-order
four bits of the PC?
Copy (4) to the left of
(3):
Is (5) the same as (1)?
0000 0000 0100 0000 0000 0000 0000 0000
00 0001 0000 0000 0000 0000 0000
0000 0100 0000 0000 0000 0000 0000
0000
0000 0000 0100 0000 0000 0000 0000 0000
Yes
Jump to absolute address
Unconditionally jump to the instruction whose
address is in register rs.
.text
.globl
__start
__start:
here:
sll
$0,$0,0
sll
$0,$0,0
sll
$0,$0,0
lui
$5,0x0040
ori
$5,0x0004
jr
$5
# Jump to 0x0040 0004
addiu
$8,$8,1
Unpredictable result
Mips states that placing branch instruction in to a
branch delay slot leads to undefined results.
__start:
lbl1:
lbl2:
sll
sll
sll
sll
j
j
j
addiu
$0,$0,0
$0,$0,0
$0,$0,0
$0,$0,0
__start
lbl1
lbl2
$8,$8,1
# OK
# Incorrect
# Incorrect