Transcript Number One
Number One Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst GITHU Processor General Purpose 32-bit, pipelined computer processor MIPS-like architecture – 24-bit address space – – Reduced instruction set 22 bits, concatenate with ending 00 32 bit boundaries 16 Registers Registers 16 Registers (ease in immediate operations) 3 Special Purpose – – – R0 – zero R14 – stack pointer R15 – return address Instruction Set Architecture First two bits indicate instruction category – 16 bit immediate built into R-type reduces complexity of design Addressing Modes – – Load, store, bra/jump, R-type Direct Indirect with Offset ISA accounts for full address space – NO PC-relative addressing Instruction Format Load / Store 31 30 29 Op(2) 24 23 Addr(6) 20 19 Rt (4) 16 15 Rs (4) 0 Address Displacement (16) R-Type 31 24 23 Opcode(8) 20 19 Rd(4) 16 15 Rs1 (4) 12 11 Rs2 (4) 0 Immediate (12) Bra / Jmp 31 30 29 Op(2) 26 25 Type(4) 24 23 Addr (2) 20 19 Rs (4) 0 Address Continued (20) Instructions Arithmetic – – – – Add Addi – add immediate Sub Subi – subtract immediate Data Transfer – – Ld - load word St – store word Instructions Logic – – – – – – – – And Andi – And immediate Or Ori – Or immediate Nor Nand Sll – logic shift left Slr – logic shift right Instructions Branches – – Beq – branch equal to zero Bne – branch not equal to zero Jumps – – Jmp – jump to specified address Jsr – jump to subroutine Interrupt handler Save current PC in register Nop – No Operation Datapath Diagram Functional Units Register File ALU Control Logic Memory System Assembler Hardware Xilinx XCV300/400/600/800 FPGA Keep FPGA on board Make PCB for all off-chip peripherals Connect two boards together via ribbon cable Processor I/O Serial RS232 port LCD, Monitor outputs Keypad, Keyboard Inputs Vital Goals Implement processor on FPGA in Verilog – – Pipelined Thorough simulation Complete Assembler Keypad, LCD I/O Make PCB with off-chip peripherals Successfully run assembly program Extended Goals On-chip caches (Instruction and data) C Compiler Monitor, Keyboard I/O Multiplier, Divider units Floating Point Units Individuals Roles Tom Bozic – Ian Nuber – ALU, PCB design Henry Romero – Assembler, control logic, test-program design Greg Ramsey – Assembler, control logic, documentation PCB design, Memory system Matt Unangst – – Pipeline implementation (forwarding, rollback) Register File Schedule Risks PCB issues (signal noise, speed, etc) – Wire wrapping Pipeline complexity – Design allows for insertion of no-ops to essentially turn machine into multi-cycle machine Questions?