Transcript 2_1_.DTU

STUDY OF
PIC MICROCONTROLLERS.
Design Flow
C CODE
Compiler
Assembly Code
Assembler
Hex File
Chip Programming
BUS Structure

Bus is a group of lines carrying digital Information
 Bus width indicates number of bit lines
 Two Types of Buses in any Processor:


Data Bus (eg: 8 bit processor has 8 bit data bus. Eg: PIC)
Address Bus (Defines the memory size)
I/O Device
Unidirectional
Address Bus
Bidirectional Data
Bus
Processor
Control Signals
Memory
Basic Micro
Computer
Bus is driven by buffers
from different devices,
processor &memory.
Ques:
How to arbitrate between
different devices that want
to access the bus at the
same time?
TRISTATE BUFFERS
Regular BUFFERS
INTRODUCTION TO MEMORIES
Memory Addressing and Access
1)Register addresses : 00,01, 10, 11
Data Bus
Processor
Input Buffer
WR
A1
Register 0
Register 1
Register 2
Register 3
Output Buffer
00
01
10
10
RD
Memory
Address
Decoder
A0
2)Active Low Wr and Read enable
signal comes from control unit
3) Additional chip select also provided if
more than one set of memory registers
available
Memory
Address
Register
[MAR]
Questions:
For a memory of 1 K byte and word size of 8 bits
1)
What is the width of MAR
2)
How many address lines come out of the decoder
3)
What is the register width
4)
What is the input/output data width ???
5)
What is the size of processor address bus
6)
What is the size of the processor data bus
DATA Transfer Unit
Main Memory location
DATA Transfer Unit
Main Memory location along with
MAR and Decoder
DATA Transfer Unit
WW : work register write
(Data bus to register)
WR: Work register read (reg
to bus)
WCLK: clock
Memory with Working Register
DATA Transfer Unit
ENHANCED DTU
(With Program Counter)
Program
memory is
separate
from data
memory
OPCODE=
instruction
codes.
ENHANCED DTU
(With Addition of Control and timing)
Status of control lines
S.
No.
RAWE
RE
WE
IE
OWE WW WR
Activity
01
0
0
0
1
0
1
0
Transfer data from input port
to working register
02
1
0
0
0
0
0
0
Write address into RAM
address register (get ready to
select an address location in
the register file)
03
0
0
1
0
0
0
1
Transfer data from working
register into the selected
RAM location
04
0
0
0
0
1
0
1
Transfer data from working
register to the output port
05
0
1
0
0
0
1
0
Transfer data from selected
RAM location into the
working register
06
0
1
0
0
1
0
0
Transfer data from selected
RAM location into the output
port
07
0
0
1
1
0
0
0
Transfer data from input port
to working register
SYSTEM CLOCK and PIPELINING
Instruction execution takes place in 2 stages , each stage needs 4 clock cycles.
Instruction Fetch and Instruction Decode
Fetch: clock1: Increment PC (PC <= PC+1) (phase 1)
clock 2,3: idle.
Clock 4: Instruction loaded in to IR
Decode:
clock 1 : Instruction decode
clock 2 : Fetch data from register or port
clock 3 :Operations carried out with data
Clock 4 :Results loaded back to destination
FETCH AND DECODE ARE INDEPENDENT. HENCE THEY CAN BE
DONE IN PARALLEL. THIS IS CALLED PIPELINING. This is a 2 stage
pipelining concept.
Instruction Cycle Pipelining
Instruction Cycle Pipelining
Machine cycle N
1
2
3
Machine cycle N+1
4
1
2
3
Machine cycle N+2
4
1
2
3
4
Increment PC
Fetch & Load
instruction into IR
Decode instruction
Fetch & execute
instruction N
Fetch data
Process data
Load results