Transcript 11 - MAL 1

Registers and MAL Part I
1
Motivation
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So far there are some details that we have
ignored
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instructions can have different formats
most computers have more than one kind of
memory
a real assembly language has no notion of data
type
Instructions as Data
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A program code can be thought of as an
array of instructions
Many modern computers, including MIPS
RISC architecture, have fixed-sized
instructions that are at least 32-bits long.
The advantage of fixed-size instructions is
the ease of calculating where it begins and
ends, especially if the size is equal to a word.
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Large instructions not only take up space but
require more time to fetch, thus there is an
advantage to small instructions.
add
opcode
a
b
c
Opcode
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The opcode corresponds to the mnemonic of
an assembly language instruction -- e.g. it
tells us that it is an add instruction.
Implicitly, it specifies how the other fields
have to be interpreted.
The opcode must be specified by a field large
enough to specify uniquely all possible codes
in the instruction set.
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How many bits do we need for the add
instruction?
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32 + 32 + 32 + 8 = 104 bits
Each memory access can only take 32 bits at
a time.
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Fetch instruction = 4 accesses
Fetch and store operands = 3 accesses
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Reducing the size of an instruction reduces
the size of the program in memory.
It also reduces the time and amount of
hardware needed to fetch the instruction.
The motivation for techniques to reduce
instruction size is based on locality of
reference property.
Locality of Reference
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A small and predictable set of variables tends
to be referenced much more often than other
variables.
This property implies that the memory is not
referenced randomly.
This property is also used to enhance speed
using a cache.
Three-address format
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A SAL instruction
add a,b,c
requires three things to be specified: The two
numbers to be added and the destination to
which the result of the addition is to be saved.
This instruction format is called a threeaddress format.
Two-address format
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The address of an instruction can often be
inferred from its context.
If we use only one specification for both the
destination of the operation result and one of
the operands, then we make the instruction
shorter.
add a,b
# a = a + b
One-address format
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We can reduce the size of the instruction
further by using an accumulator.
An accumulator is a special memory cell
used as the destination for most instruction
results.
add a #accumulator=accumulator + a
Example 11.1
The high-level language statement
a = b + c;
can be translated as:
accumulator = b
accumulator = accumulator + c
a = accumulator
Store and Load Instructions
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To assign the value of the variable x to the
accumulator we can use the instruction
lda x
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To store the value of the accumulator to x we
can use the instruction
sta x
Example 11.2
We can translate the high-level language
statement
a = b + c;
using the load and store instructions into:
lda b
add c
sta a
Example 11.3
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The use of single-address instructions need not
dramatically increase the number of instructions
as we might expect.
high-level
avg = (a + b + c + d)/ 4;
add
add
add
div
avg,a,b
avg,avg,c
avg,avg,d
avg,avg,4
SAL three-address format
lda
add
add
add
div
sta
a
b
c
d
4
avg
one-address format
Registers
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In practice, registers are designed to be a part
of the CPU and not a part of memory.
Register set or register files can be considered
as a second, small memory.
Since this is a small memory, the number of
addresses become small and thus, the number
of bits required to store the addresses reduce.
An individual word within this small memory is
called a register.
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The variables that are used more often are
assigned more or less permanently to individual
registers.
Other variables that are not used often can be
temporarily assigned to any unused register.
The values of the variables must be copied to
the register when the register is bound to the
variable and are copied back into memory when
the registers are unbound.
Hence, many variables can share the same
register in the course of the program.
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The MIPS RISC architecture get their
operands only from the registers.
The only instructions that are allowed to
access the memory are the load and store
instructions.
Architectures that restrict the access of
data in memory to load and store
instructions are called load and store
architectures.
A register is specified by preceding its
name by the symbol $.
sub $10, $8, $9
Special Registers
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Some registers are special purpose registers
like the PC (program counter) or may be use
to hold frequently used memory address like
the stack pointer.
In MIPS RISC architecture, $0 always
contains the constant 0.
Addressing Modes
The effective address is the address after
all the calculations are completed.
 Addressing mode is the method by which
an address is specified
1. Direct. Use a two-word instruction. The
address is contained in the instruction.
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opcode
reg
address
effective address
2. Register Direct. Specify a register that
contains the effective address
opcode
reg
address
effective address
3. Base Displacement/Indexed/Relative.
Specify a register and a constant. The
address is computed by adding them
together.
opcode
reg
constant
address
+
effective address
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The instruction specifies two registers
containing two addresses. The sum is the
effective address.
opcode
reg
reg
address
offset
+
effective address
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Immediate. The operand is contained
directly in the instruction.
Register. The operand is contained in a
register.
Indirect. The instruction specifies a
register which contains a first address. The
first address does not contain the operand
but contains a second address where the
operand is located.
Indirect Addressing
opcode
reg
address
address
effective address
Control Instructions
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In a load/store architecture, only two types of
instructions specify addresses:
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store and load instructions
control instructions
Control instructions specify the target
address of the next instruction if the control of
the program execution is to be transferred
there, e.g. branch, jump
PC-relative addressing
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A machine language instruction can specify an
offset to a jump.
The offset is added to the value of the PC to
find the effective address of the next
instruction. An addressing mode that implies
the use of a PC is PC-relative.
beq
program
counter (PC)
var1
address
var2
offset
+
effective address