Lecture 12 Revision Midterm 2 - Department of Computer Science

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Transcript Lecture 12 Revision Midterm 2 - Department of Computer Science

Midterm 2 Revision 2
Prof. Sin-Min Lee
Department of Computer Science
Subtract by Summation
• Subtraction with complement is done with
binary numbers in a similar way.
• Using two binary numbers X=1010100 and
Y=1000011
• We perform X-Y and Y-X
X-Y
•
•
•
•
X=
2’s com. of Y=
Sum=
Answer=
1010100
0111101
10010001
0010001
Y-X
• Y=
• 2’s com. of X=
• Sum=
1000011
0101100
1101111
• There’s no end carry: answer is negative --0010001 (2’s complement of 1101111)
How To Represent Signed Numbers
•
Plus and minus signs used for decimal numbers: 25
(or +25), -16, etc.
•
For computers, it is desirable to represent everything
as bits.
•
1.
2.
3.
Three types of signed binary number representations:
signed magnitude,
1’s complement, and
2’s complement
1. signed magnitude
• In each case: left-most bit indicates sign:
positive (0) or negative (1).
Consider 1. signed magnitude:
000011002 = 1210
Sign bit
Magnitude
100011002 = -1210
Sign bit
Magnitude
2. One’s Complement
Representation
• The one’s complement of a binary
number involves inverting all bits.
• To find negative of 1’s complement number take the 1’s
complement of whole number including the sign bit.
000011002 = 1210
Sign bit
Magnitude
111100112 = -1210
Sign bit
1’complement
3. Two’s Complement
Representation
• The two’s complement of a binary number
involves inverting all bits and adding 1.
• To find the negative of a signed number take
the 2’s the 2’s complement of the positive
number including the sign bit.
000011002 = 1210
Sign bit
Magnitude
111101002 = -1210
Sign bit
2’s complement
Sign addition in 2’s complement
The rule for addition is add the two numbers, including their sign bits,
and discard any carry out of the sign (leftmost) bit position.
Numerical examples for addition are shown below.
Example:
+6
00000110 - 6 11111010
+13
00001101 +13 00001101
+19
00010011 +7
00000111
+6
00000110 -6
11111010
-13
11110011
-13
11110011
-7
11111001 -19
11101101
In each of the four cases, the operation performed is always addition,
including the sign bits.
Only one rule for addition, no separate treatment of subtraction.
Negative numbers are always represented in 2’s complement.
Arithmetic Subtraction
• A subtraction operation can be changed to
an addition operation if the sign of the
subtrahend is changed.
• (±A) - (+B) = (±A) + (-B)
• (±A) - (-B) = (±A) + (+B)
Arithmetic Subtraction
• Consider the subtraction of (-6) - (-13) = +7. In
binary with eight bits this is written as 11111010 11110011. The subtraction is changed to addition
by taking the 2’s complement of the subtrahend (13) to give (+13). In binary this is 11111010 +
00001101 = 100000111.
• Removing the end carry, we obtain the correct
answer 00000111 (+ 7).
Overflow
• The detection of an overflow after the addition of two
binary numbers depends on whether the considered
numbers are signed or unsigned.
• When two unsigned numbers are added, an overflow is
detected from the end carry out of the most significant
position.
• In the case of signed numbers, the leftmost bit always
represents the sign, and negative numbers are in 2’s
complement form.
• When two signed numbers are added, the sign bit is treated
as part of the number and the end carry does not indicate
an overflow.
Overflow
• Overflow example:
+70 0 1000110
+80 0 1010000
= +150 1 0010110
-70
-80
1 0111010
1 0110000
=-150 0 1101010
Overflow
• An overflow cannot occur after an addition if one
number is positive and the other is negative, since
adding a positive number to a negative number
produces a result that is smaller than the larger of
the two original numbers.
• An overflow may occur if the two numbers added
are both either positive or negative.
Some commonly used components
• Decoders: n inputs, 2n outputs.
– the inputs are used to select which output is
turned on. At any time exactly one output is on.
• Multiplexors: 2n inputs, n selection bits, 1
output.
– the selection bits determine which input will
become the output.
• Adder: 2n inputs, 2n outputs.
– Computer Arithmetic.
Multiplexer
• “Selects” binary information from one of many
input lines and directs it to a single output line.
• Also known as the “selector” circuit,
• Selection is controlled by a particular set of inputs
lines whose # depends on the # of the data input
lines.
• For a 2n-to-1 multiplexer, there are 2n data input
lines and n selection lines whose bit combination
determines which input is selected.
MUX
Enable
2n Data
Inputs
Data
Output
n
Input
Select
Remember the 2 – 4 Decoder?
Sel(3)
S1
Sel(2)
Sel(1)
S0
Sel(0)
Mutually Exclusive
(Only one O/P asserted at
any time
4 to 1 MUX
DataFlow
D3:D0
Dout
4
Control
2-4
Decoder
2
S1:S0
4
Sel(3:0)
4-to-1 MUX (Gate level)
Control Section
Three of these signal
inputs will always be 0. The
other will depend on the
data value selected
Multiplexer (cont.)
• Until now, we have examined single-bit
data selected by a MUX. What if we want
to select m-bit data/words?
 Combine MUX blocks in parallel with
common select and enable signals
• Example: Construct a logic circuit that
selects between 2 sets of 4-bit inputs (see
next slide for solution).
Example: Quad 2-to-1 MUX
• Uses four 4-to-1
MUXs with common
select (S) and enable
(E).
• Select line chooses
between Ai’s and Bi’s.
The selected fourwire digital signal is
sent to the Yi’s
• Enable line turns
MUX on and off (E=1
is on).
Implementing Boolean functions
with Multiplexers
• Any Boolean function of n variables can be
implemented using a 2n-1-to-1 multiplexer. A
MUX is basically a decoder with outputs
ORed together, hence this isn’t surprising.
• The SELECT signals generate the minterms of
the function.
• The data inputs identify which minterms are to
be combined with an OR.
Example
•F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)
•There are n=3 inputs, thus we need a 22-to-1 MUX
•The first n-1 (=2) inputs serve as the selection lines
Efficient Method for
implementing Boolean functions
• For an n-variable function (e.g., f(A,B,C,D)):
– Need a 2n-1 line MUX with n-1 select lines.
– Enumerate function as a truth table with consistent
ordering of variables (e.g., A,B,C,D)
– Attach the most significant n-1 variables to the n-1
select lines (e.g., A,B,C)
– Examine pairs of adjacent rows (only the least
significant variable differs, e.g., D=0 and D=1).
– Determine whether the function output for the
(A,B,C,0) and (A,B,C,1) combination is (0,0), (0,1),
(1,0), or (1,1).
– Attach 0, D, D’, or 1 to the data input corresponding to
(A,B,C) respectively.
Another Example
• Consider F(A,B,C) = m(1,3,5,6). We can
implement this function using a 4-to-1
MUX as follows.
• The index is ABC. Apply A and B to the S1
and S0 selection inputs of the MUX (A is
most sig, S1 is most sig.)
• Enumerate function in a truth table.
MUX Example (cont.)
A
B
C
F
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
When A=1, B=0, F=C
1
0
0
0
1
0
1
1
When A=B=1, F=C’
1
1
0
1
1
1
1
0
When A=B=0, F=C
When A=0, B=1, F=C
MUX implementation of
F(A,B,C) = m(1,3,5,6)
A
B
C
C
C
C’
F
These pictures have errors.
1 input Decoder
I
Decoder
O0
O1
Treat I as a 1 bit integer i. The ith output will be
turned on (Oi=1), the other one off.
1 input Decoder
I
O0
O1
2 input Decoder
O0
I0
Decoder
I1
O1
O2
O3
Treat I0I1 as a 2 bit integer i. The ith output will
be turned on (Oi=1), all the others off.
2 input Decoder
I0 I1
O0 = !I0 && !I1
O1 = !I0 && I1
O2 = I0 && !I1
O3 = I0 && I1
3 Input Decoder
O0
I0
O1
O2
I1
Decoder
I2
O3
O4
O5
O6
O7
3-Decoder Partial Implementation
I0 I1 I2
O0
O1
...
2 Input Multiplexor
Inputs: I0 and I1
Selector: S
Output: O
If S is a 0: O=I0
If S is a 1: O=I1
I0
Mux
I1
S
O
2-Mux Logic Design
S
I0 I1
I0 && !S
O
I1 && S
4 Input Multiplexor
Inputs: I0 I1 I2 I3
Selectors: S0 S1
Output: O
S0 S1
0 0
0 1
1 0
1 1
O
I0
I1
I2
I3
I0
I1
I2
Mux
I3
S0 S1
O
One Possible 4-Mux
S0
S1
I0
2-Decoder
I1
I2
I3
O
Adder
• We want to build a box that can add two 32
bit numbers.
– Assume 2s complement representation
• We can start by building a 1 bit adder.
Addition
• We need to build a 1 bit adder
– compute binary addition of 2 bits.
• We already know that the result is 2 bits.
A
0
0
1
1
B
0
1
0
1
O0
0
0
0
1
O1
0
1
1
0
This is addition!
A
+ B
O0 O1
One Implementation
A && B
A
B
O0
!A
B
A
!B
(!A && B) || (A && !B)
O1
Binary addition and our adder
1
+
1
01001
01101
10110
Carry
What we really want is something that can be
used to implement the binary addition
algorithm.
– O0 is the carry
– O1 is the sum
What about the second column?
1
+
1
01001
01101
10110
Carry
• We are adding 3 bits
– new bit is the carry from the first column.
– The output is still 2 bits, a sum and a carry
Truth Table for Addition
A
B
Carry Carry
In
Out
Sum
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
1
1
1
1
0
1
1
1
0
1
Synchronous Sequential Circuit with T Flip-Flop --
z
x
y
y
Q
Q
T
C
Figure 8.12
Clock
Timing Diagram
Clock
x
0
1
1
0
1
0
0
0
y
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
0
1
2
3
4
5
6
7
8
T
z
0
Figure 8.13
State Table and State Diagram
xk
xk
0
yk
1
yk 0
1
0
1
yk + 1/zk
xk
0
1
1/0
0/0
1/0
0/1
Present
state
yk + 1/zk
(a)
0/0
B
1/1
(d)
A
B/0
A/0
B
B/0
A/1
(c)
x/
z
A
1
Next state/output
(b)
1/0
0
0/0
K-Maps for Example
xk
0
xk
0
1
0
0
k
0
xk
0
1
1
0
k
y
0
0
1*
0
1
1
0*
y
1
1
1
k
y
1
0
0
1
zk
Tk
yk + 1
(a)
(b)
(c)
xk
0
1
0
1/0
0/0
1
1/0
0/1
yk
yk + 1/zk
(d)
Example 2.Synchronous Sequential Circuit with JK
Flip-flops
z
J1
Q
y1
C
K1
Q
J2
Q
y2
Q
y2
y1
x
C
K2
Clock
Timing Diagram and State Table for Example 2
C
x
0
0
1
1
1
1
0 0
y1
1
0
0
0
1
1
1 0
y2
0
0
0
1
0
1
1 0
0
0
0
0
0
1
0 0
J1 = xy2
K1 = x
J2 = x
K2 = x + y1
z = xy1 y2
(a)
x
y1 y2
0
1
00 00/0 01/0
01 00/0 10/0
11 00/0 11/1
10 00/0 11/0
(b)
K-Maps for Example 2
x
y1 y2
x
0
1
00
0
0
01
0
11
10
y1 y2
0
1
00
1
0
1
01
1
0
0
1
11
1
0
0
0
10
1
0
J1
K1
x
y1 y2
x
0
1
00
0
1
01
0
11
10
y1 y2
x
0
1
00
1
1
1
01
1
0
1
11
0
1
10
J2
y1 y2
0
1
00
0
0
1
01
0
0
1
0
11
0
1
1
0
10
0
0
K2
z
Generating the State Table From K-maps -Example 2
x
y 1 y2
00
01
0
01
01
1
01
01
00
10
11
11
11
01
01
10
10
10
01
01
00
10
J1 K1 J2 K2 J1 K1 J2 K2
(a)
y1 y 2
x
y 1 y2
x
0
1
00
00
01
00
00/0 01/0
01
00
10
01
00/0 10/0
11
00
11
11
00/0 11/1
10
00
11
10
00/0 11/0
Y1 Y2
(b)
0
1
Y1 Y2/z
(c)
Example 3.Synchronous Sequential Circuit Synthesis
x
A
1/0
1/1
1/0
0/0
0/0
0/0
D
0/0
B
1/0
C
0
1
A
D/0
B/0
B
D/0
C/0
C
D/0
B/0
D
D/0
A/1
(a) Completely specified circuit
x
1/1
A
0/-
0/1/C
B
1/1
0
1
A
B/-
-/1
B
B/0
C/1
C
A/-
A/-
0/0
(b) Incompletely specified circuit
Introductory Synthesis Example -- Example 3
x
x
y1 y 2
z
x
0
1
A
A/0
B/0
A
0 0
00
00/0 01/0
B
A/0
C/1
B
0 1
01
00/0 11/1
C
B/0
D/0
C
1 1
11
01/0 10/0
D
C/1
D/0
D
1 0
10
11/1 10/0
State
00
x
x
0
1
y1 y2
0
1
0
0
00
0
0
0
1
Y1 Y2/z
(c)Transition
table
(b) State
assignment
(a) State table
y1 y2
y1 y2
y1 y2
x
00
0
1
0
1
y1
01
0
1
01
0
1
01
0
1
11
0
0
11
0
1
11
1
0
10
1
0
10
1
1
10
1
0
z
(d) Output K-map
D1 (= Y1)
y1
D2 (= Y2)
(e) Excitation K-maps
y2
y2
Q
D1
Q
C
Q
D2
Q
C
(f) Logic diagram
Clock
Flip-flop Input Tables -- Example 3
State
Required
transitions
inputs
Q(t) Q(t + e)
D(t)
State
transitions
Q(t) Q(t + e)
Required
inputs
S(t)
R(t)
0
0
0
0
0
0
d
0
1
1
0
1
1
0
1
0
0
1
0
0
1
1
1
1
1
1
d
0
(a) D flip-flop
(b) Clocked SR
State
Required
transitions
inputs
Q(t) Q(t + e)
T(t)
State
transitions
Q(t) Q(t + e)
Required
inputs
J(t)
K(t)
0
0
0
0
0
0
d
0
1
1
0
1
1
d
1
0
1
1
0
d
1
1
1
0
1
1
d
0
(c) Clocked T flip-flop
(d) Clocked JK flip-flop
Generating the JK Flip-flop Excitation Maps -Example 3
y1 y2
x
0
y1 y2
1
x
0
x
1
00
0
0
01
0
11
10
1
00 0d
0d
00 0d
1d
01 0d
1d
01 d1
d0
11 01/0 10/0
11 d1
d0
11 d0
d1
10 11/1 10/0
10 d0
d0
10 1d
0d
J1K1
y1 y2
J2K2
(b) Excitation table
x
0
1
00
d
d
1
01
d
d
d
11
d
d
10
J1
0
01 00/0 11/1
Y1 Y2/z
0
x
00 00/0 01/0
(a) Transition table
y1 y2
y 1 y2
1
y1 y2
x
0
1
00
0
1
d
01
d
1
0
11
0
0
10
K1
x
0
1
00
d
d
d
01
1
0
d
d
11
0
1
1
0
10
d
d
J2
(c) Excitation maps
y1 y 2
K2
Clocked JK Flip-Flop Implementation -Example 3
x
z
y1
y1
y2
y2
Q
J1
Q
C
K1
Q
Q
J2
C
K2
Clock
Application Equation Method for Deriving
Excitation Equations -- Example 3
x
x
y1 y2
0
1
00
0
0
01
0
1
y1 y2
0
1
00
0
1
01
0
1
y2
11
1
0
11
1
0
10
1
0
y1
10
1
1
Y1
Y2
Registers
• Two independent flip-flops with clear and preset