Transcript C q

Development of front-end electronics for
Silicon Photo-Multipliers
F. Corsi, A. Dragone, M. Foresta, C. Marzocca, G. Matarrese, A. Perrotta
INFN DASiPM Collaboration
DEE - Politecnico di Bari and INFN Bari Section, Italy
Main activities
•
Accurate modelling of the SiPM for reliable simulations at circuit level.
•
Development of an extraction procedure for the parameters involved in the model.
•
Validation of the model accuracy.
•
Comparison of different front-end approaches.
•
Preliminary results of the first version of front-end based on a current buffer .
Electrical model of a SiPM
Rq: quenching resistor
(hundreds of kW)
Cd: photodiode capacitance
(few tens of fF)
Cq: parasitic capacitance in
parallel to Rq (smaller than Cd)
IAV: current source modelling the
total charge delivered by a
microcell during the avalanche
 Cg : parasitic capacitance due to the routing of the bias voltage to the N microcells, realized with
a metal grid.
Example: metal-substrate unit area capacitance 0.03 fF/mm2
metal grid = 35% of the total detector area = 1mm2
Cg  10pF, without considering the
fringe parasitics
 Avalanche time constants much faster than those introduced by the circuit:
IAV can be approximated as a short pulse containing the total amount of charge delivered by the
firing microcell Q=DV(Cd+Cq), with DV=VBIAS-VBR
Extraction of Rq
Forward characteristic of the SiPM, region in which DV/DI is almost constant and equal to Rq/N.
_____
_____
Measured characteristic
Least square linear fit
Forward characteristic of a SiPM
produced by ITC-irst.
Slope = 1.59 mS
Rq/N = 629 W
N = 625
Rq = 393 kW
Extraction of Vbr and Cd+Cq
Charge associated to a single dark count pulse as a function of the bias voltage:
Q=(Cd+Cq)(Vbias-Vbr)
Cd+Cq and, by extrapolation, Vbr
*
Least square linear fit
Q [C]
__
Measured points
Vbias [V]
Example of a single dark count pulse for
the ITC-irst SiPM (obtained by reading the
pulse with a 50W resistor and using a 140
gain, fast voltage amplifier)
Charge contained in a single dark count
pulse vs. bias voltage
Extraction of Cd, Cq and Cg
 CV plotter measurements near the breakdown voltage: YM and CM
CV plotter measurement results for
the same device from ITC-irst. The
signal frequency is 1 MHz.
CM [pF]
YM [mS]
 According to the SiPM model, YM and CM are expressed in terms of Cdtot=NCd, Cqtot=NCq, Rqtot=Rq/N
and the frequency w of the signal used by the CV plotter.
Vbias [V]
YM
CM
Rqtot
Vbias [V]
YM 
Cqtot
Cg
Cdtot
CM 
2
w2 R qtotC dtot
1 w
2
C
R qtotC 2t
t
 C dtot  C qtot

2
C dtot  C g  w2 R qtot
C t (C g C t  C qtotC dtot )
1 w
2
2
R qtot
C 2t
Cd,Cq
Cg
Results of the extraction procedure
 Extraction procedure applied to two SiPM detectors from different manufacturers.
 The table summarizes the main features of the devices and the results obtained.
 Good agreement with the expected parameter values estimated on the basis of
technological and geometrical parameters.
Model Parameter
SiPM ITC-irst
N=625, Vbias=35V
SiPM Photonique
N=516, Vbias=63V
Rq
393 kΩ
774 kΩ
Vbr
31.2 V
61 V
Q
175.5 fC
127.1 fC
Cd
34.6 fF
40.8 fF
Cq
12.2 fF
21.2 fF
Cg
27.8 pF
18.1 pF
Front-end electronics: different approaches
Vbias
Vbias
Vbias
CF
SiPM
SiPM
+
VOUT
Charge sensitive amplifier
RS
SiPM
+
-
VOUT
Voltage amplifier
RS
IS
kIS=IOUT
Current buffer
The charge Q delivered by the
detector is collected on CF
A I-V conversion is realized by
means of RS
RS is the (small) input impedance of
the current buffer
If the maximum DVOUT is 3V and Q
is 50pC (about 300 SiPM
microcells), CF must be 16.7pF
The value of RS affects the gain and
the signal waveform
The output current can be easily
reproduced (by means of current
mirrors) and further processed (e.g.
integrated)
Perspective limitations in dynamic
range and die area with low voltage,
deep submicron technologies
VOUT must be integrated to extract
the charge information: thus a
further V-I conversion is needed
The circuit is inherently fast
The current mode of operation
enhances the dynamic range, since
it does not suffer from voltage
limitations due to deep submicron
implementation
SiPM + front-end behaviour
IIN
Cq
Rq
(N-1)Cq
Rq/(N-1)
Cg
The load effects, the grid parasitic capacitance
and the value of Rs are key factors in the
determination of the resulting waveform of VIN
and IIN
+
RS
VIN
Cd
IAV
A qualitative study of the circuit can be carried
out with reference to the simplified schematic
depicted below. The two circuits give very
similar results, provided that Rs is much lower
than Rqtot=NRq
(N-1)Cd
A) SiPM coupled to an amplifier with
input impedance Rs
IIN
IAV
Cd
Cq
Rq
Iq
Ceq
Cg
RS
+
VIN
Iq
B) Simplified circuit
1
1
1


C eq ( N  1)C d ( N  1)C q
SiPM + front-end behaviour
1.0mV
_____
Circuit A)
_____
Circuit B)
The simulations show that the peak of VIN is
almost independent of Rs.
In fact, a constant fraction QIN of the charge Q
delivered during the avalanche (considered
very fast with respect to the time constants of
the circuit) is instantly collected on Ctot=Cg+Ceq.
VIN
Rs=75W
0.5mV
The simplified circuit has two time constants:
Rs=50W
• tIN= Rs Ctot
• tr=Rq(Cd+Cq)
0V
Rs=20W
0s
20ns
V(Rin:2)
40ns
V(C1:2,Vbias)
60ns
80ns
100ns
Time
Time
Responses of the circuits A) and B) to a single dark pulse (160fC)
for three different values of Rs and typical parameter values
VIN (t ) 
t r  tq
QR S  tq  tIN
t
t 

exp(
)
exp( ) 
tr  tIN  tIN
tIN
tr
tr 
t
q
 R q Cq

Decreasing Rs, the time constant tIN decreases,
the current in Rs increases and the collection of
the charge is slightly faster, as shown by the
simulations.
Q IN  Q
Cq
Cd  Cq
VINMAX 
Q IN
C tot
Bandwidth of the amplifier
BW=500MHz
_____
BW=500MHz
_____
BW=100MHz
_____
BW=100MHz
VOUT
40.0mV
100mV
_____
VOUT
55.3mV
50mV
Rs=75W
Rs=20W
20.0mV
0V
0V
0s
10ns
20ns
30ns
V(R2:2)
40ns
50ns
60ns
0s
10ns
20ns
30ns
40ns
50ns
60ns
V(R2:2)
Time
Time
Time
Time
Amplifier output voltage for a single dark pulse: same gain and different bandwidth
• The simulations show the output of a voltage amplifier for two different Rs and bandwidths.
• The bandwidth of the amplifier directly affects the rise time of the waveform, independently of the value of RS.
• The peak amplitude of the waveform is strongly dependent on the amplifier bandwidth, especially for low values of RS.
In fact, in this case tIN can be very fast compared to the dominant time constant of the amplifier, which is unable to
adequately reproduce the input signal.
• The time needed to collect the charge is just slightly influenced by the amplifier bandwidth.
• The same conclusions are valid also for the waveform of the output current obtained with a current buffer
Experimental validation of the model
Two different amplifiers have been used to read-out the ITC-irst SiPM
a)
Transimpedance amplifier
BW=80MHz Rs=110W Gain=2.7kW
b)
Voltage amplifier
BW=360MHz Rs=50W Gain=140
• The model extracted according to the procedure described above has been used in the SPICE simulations
• The fitting between simulations and measurements is quite good
Current buffer: two alternative solutions
Buffer2
Buffer1
• CMOS 0.35um standard technology
• Feedback applied to reduce input resistance and increase bandwidth
Integrated current buffer: two alternative solutions
Buffer1
Buffer2
• simple structure
• more complex
• more bandwidth (≈ 300 MHz)
• a little slower (BW 250 MHz)
• limited dynamic range
• extended dynamic range
Experimental
setup
Experimental setup
Current
Buffer
50Ω
Pulse
Generator
Blue
Led
SiPM
100Ω
Vbias
V
Test board
Input waveform
8ns
7V
4.5ns
Voltage
Amplifier
4.5ns
t
Iout
BNC
Preliminary
Measure results: dark count pulses
Preliminary
Measure results: output waveforms
4.5
2
Vbias [V]
31.5
32
32.5
33
33.5
34
31.5
32
32.5
33
33.5
34
34.5
35
35.5
3.5
3
Iout [mA]
Iout [mA]
1.5
Vbias [V]
4
1
2.5
2
1.5
0.5
1
0.5
0
0
20
40
60
80
100
120
Time [ns]
Buffer1
140
160
180
200
0
0
20
40
60
80
100
120
Time [ns]
140
160
180
200
Buffer2
• The test board is the bottleneck for the BW of the whole system
• The total no. of photons is always the same in all measurements
• The standard deviation of the current peak corresponds to about 1/2 micro-cell
Preliminary
Measure results: linearity
4.5
First solution
Second solution
4
3.5
Ipeak [mA]
3
2.5
2
1.5
1
0.5
31.5
32
32.5
33
33.5
Vbias [V]
34
34.5
35
35.5
• The first solution exhibits limited dynamic range and gain, as expected
Future
work
Measure
• More measurements on the current buffers with known ligth source
• Definition of the architecture (shaper?
current peak detector? on chip ADC?)
• 9 channel test chip
• Migration to another technology (for instance 0.18um)
• Final task: 64 channel ASIC