Transcript UB Power system

U.B. Presentation
October 2001 - Bernard COURTY
L.P.C.C. College de France - Paris
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
POWER SYSTEM :
 Temperature range : -20 C to +70 C
 Input range : 19 to 30 VDC
Voltage P Nom
P Max
Accuracy
12 V
5V
4W
2W
7W
3W
1%
2%
+3,3V
+/-3,3V
6W
7.2 W
5%
0.5 W
1W
1%
(per supply)
 Efficiency : 80 - 84 %
Ripple&Noise
@20 MHz
Destination
PMT
bases,
50 mV
telecom.
50 mV
SC, Eth
Digital
50 mV
electronic
20 mV
FE (Analog. Elec.)
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
 Note that some devices are powered through a
cable degrading the above conditions
 2 solutions studied : custom or separate
 Common ground
 Protection Vs over voltage (35V) and inverted
connection
 Protection for fuses (may be resetable but still
need human intervention)
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
 Automatic system supply shutdown when :
* Temperature is too high (e.g. if t > 70C)
* Voltage is lower or higher than a specified
range value
 CPU is informed about the problem 60 second
before power system shut down
 Duration of shutdown is fixed to 3 hours
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
UNIFIED BOARD :
 CPU power PC 403 GCX
 80 Mhz core / 40 Mhz external
 32 bits data and 32 bits adress
 32 Mo DRAM EDO
 4 Mo In system programmable flash EPROM
 Box temp. must be less than 40 deg. C.
 Connector for Ethernet interface (development, debugging)
with presence detection)
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
 In system programmable PLD to enhance
flexibility
 Enhanced protection for GPS module and coms
interface (EA trouble)
 LED module soldering (2 LED channels)
 4 standards DB9 serial ports
 20 years minimum life time required
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
CONNECTORS :
The front panel connectors will be as below :
 Radio serial : DB9 female
 Console serial : DB9 male
 TPCB serial : DB9 male
 Spare serial : DB9 male
 PMT power (*3) : 3 DB15 HD female
 Sensor cable : DB15 HD female
 PMT anode and dynode inputs : SMA female on FE, 6
total)
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
 Led driver outputs : 2 SMA female on Led driver board
 Power connector (24 Vcc) with to pins
 Grounding plug on box exterior
TIME TAGGING :
Problems with Asic time tagging has been fixed (the TTG ASIC is now
perfectly working) :
 There was glitch problems on the bus and off course on the
time tagging test board
 We always plan to have 2 footprints for pre-production :
*one for the Asic
*the other for the ACEX FPGA
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
Explanations about the problem on the ASIC time tagging :
 The problem of "permanent" reset was effective , BUT NOT
DUE TO INTERNAL or LAYOUT or SHORT INSIDE the
CHIP. The problem was comming from parasitics on some
signals on the BUS and on the TTG PCB board . This produces
very narrow (2ns) parasitics pulses that acts as reset of the chip
and which were very difficult to see.
This problem was overcome simply with one damping resistor on
the related signal .
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
SLOW CONTROL :
Monitoring are :
 3 PMT temperature
 3 PMT high voltage monitor
 3 PMT current monitor
 1 unified board temperature
 4 unified board voltages :
*battery input (24-28 volts)
*12 volts, 5 volts and 3volts3 digital
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
 2 spares (water temperature + water level?)
 ADC : 32 channels become 16 (14 channels busy+2spares)
 DAC : 8 channels become 4
 Digital outputs : 16 channels become 4
 Digital inputs : 16 channels become 0
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
OPEN QUESTIONS :
 Is it Ok for PLD programming method ?
 Do we need a power switch ? (inside the box ?)
 Tropicalising connection between modules after soldering ?
 Temperature and humidity issue ?
 Precision on UB mounting/dismounting, need for UB PCB
mechanical features ?
 Is there power supply constraints for SC ?
 Did EA show that everything is fine on SC ? Noise ?
 PMT bases people asked to have a 100 kohms load on the ADC inputs
to avoid oscillating, is it a problem ?
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
 Will we use the same GPS module (provisioning)?
 Jim was preparing a small filtering device to be inserted between CPU
and GPS to reduce the conductive interference. Was it efficient?
Should we insert that on the U.B. ?
 ADC input ESD protection ?
 DAC output protection ?
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
 Quality insurance :
In our public tender we have asked for the ISO 9000 quality
insurance (or equivalent),
technical and man power resources, tests procedures,
production logging system and boards backtracking.
 The boards reliability is defined by the MIL-HDBK-217F
standard (ground fixed conditions)
 The MTBF index is determined and must be equal to the
Auger life time.
L.P.C.C. C.D.F. - Malargue Meeting - October 2001
Short schedule :
 Public tender published in August 2001.
 Juanary 2002 : first UB prototype / factory selection (public tender)
 March/April 2002 : 10 first industrials prototype
 September 2002 : pre-production 120 UB
 April to September 2003 : production of 900 UB
 May to October 2004 : production of 800 UB
This schedule depend on :
 We must define all UB specifications
 Prototypes testing approbation
 Component availability
 Budget possibility
 Factory disponibility