Transcript Slide 1

DIGITAL SYSTEMS TCE1111
INTERFACING WITH ANALOG
DEVICES
(Week 12)
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DIGITAL SIGNAL PROCESSING BASICS
Digital signal processing converts signals that naturally occur in
analog form, such as sound, video and information form sensors,
to digital form and uses digital techniques to enhance and modify
analog signal data for various applications.
A digital system processing system first translates a smoothly
varying analog signal into a series of discrete levels. This series of
levels follows the variations of the analog signal and resembles a
staircase ,as illustrated in Fig 1.This is accomplished by sample
and hold circuits.
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DIGITAL SIGNAL PROCESSING BASICS
An original analog signal (sine wave) and its “stairstep” approximation.
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DIGITAL SIGNAL PROCESSING BASICScont..
• Next, the stair step approximation is quantized into binary
codes that represent each discrete step on the stair steps by a
process called analog-to-digital conversion (ADC).
• The binary codes are then applied to Digital signal processor
(DSP) which performs various operations on the incoming
data ,such as removing unwanted interference, increasing the
amplitude of some signal frequencies etc.
• After the DSP processes the signal, it can be converted back to
a much improved version of the original analog signal by
digital to analog converter (DAC).
• Fig 2 shows a basic block diagram of a typical DSP system.
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DIGITAL SIGNAL PROCESSING BASICScont..
Fig 2 Basic block diagram of a digital signal processing system.
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Converting Analog signals to Digital
Filtering and sampling
Sampling is the process of taking a sufficient number of
discrete values at points on a waveform that will define
a waveform. Sampling converts an analog signal into a
series of impulses, each representing the amplitude of
the signal at a given instant in time.
Before a signal can be sampled, it must be passed
through a low-pass filter to eliminate harmonic
frequencies .
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Converting Analog signals to Digital
Holding the sampled value
After filtering and sampling ,the sampled level must be
held constant until the next sample occurs. This is
necessary for the ADC to have time to process the
sampled value.
This sample and hold operation results in a stair step
waveform that approximates the analog input waveform,
as shown in fig 3.
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Converting Analog signals to Digital
fig 3 Illustration of a sample-and-hold operation.
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Analog to Digital conversion
Analog –to-digital conversion is the process of
converting the output of the sample and hold circuit to a
series of binary codes that represent the amplitude of the
analog input at each of the sample times.
The sample and hold process keeps the amplitude of the
analog input signal between sample pulses.
Fig 4 illustrates the basic function of a ADC converter.
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Analog to Digital conversion
Figure 4 Basic function of an analog-to-digital (ADC) converter (The binary
codes and number of bits are arbitrarily chosen for illustration only). The ADC
output waveform that represents the binary codes is also shown .
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Quantization
The process of converting an analog value to a
code is called quantization. The ADC converts
each sampled value of the analog signal to a
binary code.
The Quantization operation is illustrated in fig 5.
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Figure 5 Sample-and-hold output waveform with four quantization levels.
The original analog waveform is shown in light gray for reference.
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Analog –to Digital Conversion MethodsFLASH (SIMULTANEOUS ) ADC CONVERTER (1)…
The flash method utilizes comparators that compare reference
voltage with the analog input voltage. When the input voltage
exceeds the reference voltage ,a HIGH is generated. A comparator
is not needed for all 0’s condition. In general a
2n -1 comparators are required for converting to an n- bit binary
code. The number of bits in an ADC is its resolution.
Advantage:
Provides a fast conversion times because of a high through put
measured in sps (samples per second.)
Disadvantage:
Large number of comparators necessary for a reasonable –sized
binary number
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FLASH (SIMULTANEOUS ) ADC CONVERTER (2)…
Figure 6 A 3-bit flash ADC
C7
C6
C5
C4
C3
C2
C1
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FLASH (SIMULTANEOUS ) ADC CONVERTER (3)… Operation of 3bit flash ADC
• The flash method utilizes comparators that compare reference voltages with the
analog input voltage. When the input voltage exceeds the reference voltage for
a given comparator, a HIGH is generated.
• The reference voltage for each comparator is set by the resistive voltagedivider circuit. The output of each comparator is connected to an input of the 8input priority encoder.
• The encoder is enabled by a pulse on the EN input, and a 3-bit code
representing the value of the input appears on the encoder’s outputs. The binary
code is determined by the highest order input having a HIGH level.
• Assume the step size of 1 V. The voltage divider sets up reference levels for
each comparator so that there are 3 levels corresponding to 1V, 2V, 3V, 4V, 5V,
6V and 7V. The analog input is connected to other input of each comparator.
• With analog input <1V, all the seven comparator outputs will be LOW.
Suppose the analog input is between 2V and 3V, outputs C1 and C2 will be
HIGH. The priority encoder will respond to HIGH on C2, and will produce a
binary output of 010.
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FLASH (SIMULTANEOUS ) ADC CONVERTER (4)… Example-3-bit
Flash ADC
Determine the binary code output of the 3-bit Flash ADC for the input signal
And the encoder enable pulses as shown below. Assume VREF=+8V
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FLASH (SIMULTANEOUS ) ADC CONVERTER (5)
Solution -3-bit Flash ADC
The resulting digital output sequence: 100 (4) ,110(6),111(7),110(6),
100 (4), 010(2), 000(0), 001(1), 011 (3),101 (5),110 (6), 111(7)
Waveform of the resulting digital output sequence:
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Dual Slope ADC (1)…
A dual slope ADC is common in digital voltmeters and other type of measurement instruments.
A block diagram of dual slope ADC is shown in fig 7.
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Dual Slope ADC (2)…
Assume that the counter is reset and the
integrator output is zero. A positive input voltage
is applied to the input through the switch as
selected by control logic.
• Since the inverting input of A1 is at virtual
ground, and assuming that Vin is constant for a
period of time , there will be constant current
through the input resistor R and through the
capacitor C. Capacitor will charge linearly
because the current is constant and as a result the
will be a negative going linear voltage ramp on
the output of A1
•
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Dual Slope ADC (3)…
•
When the counter reaches a specified count , it will
be reset and the control logic will switch the negative
reference voltage (-Vref ) to the input of A1 . At this
point the capacitor is charged to a negative voltage (-v)
proportional to input analog voltage.
•
Now the capacitor discharges linearly because of the
constant current from the –Vref .This linear discharge
produce a positive going ramp on the A1 output ,
starting at –v and having a constant slope that is
independent of the charge voltage.
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Dual Slope ADC (4)…
As the capacitor discharges, the counter
advances from its RESET state. The time it takes
the capacitor to discharge to 0 depends on the
initial voltage –V. When A1 reaches 0 , A2
switches to low state and disables the clock to the
counter
• The binary count is latched thus completing one
conversion cycle. The binary count is
proportional to Vin. .This process is illustrated in
Fig 8.
•
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Dual Slope ADC (5)
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Successive - approximation ADC (1)…
Fig 9 shows the basic block diagram of a 4 bit Successive - approximation ADC . It consists
of a DAC, Successive-Approximation Register (SAR), and a comparator
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Successive - approximation ADC (2)… Basic operation
•
•
•
•
•
•
The input bits of the DAC are enabled one at a time starting
with the MSB
As each bit is enabled the comparator produces an output that
indicate whether the input signal voltage is greater or lesser than
the output of DAC.
If the DAC output is greater than the input signal ,the
comparator’s output is LOW, causing the bit in the register to
reset.
If the DAC output is less than the input signal, the bit 1 is
retained in the register.
The system does this with the MSB first, then the next right bit of
MSB, then the next and so on.
After all the bits in the DAC are tried , the conversion cycle is
complete.
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Successive - approximation ADC (3)…
Illustration of Basic operation with an example
• Assume that the DAC has the following output characteristics:
Vout=8V for the 23 bit (MSB),
Vout =4V for the 22 bit,
Vout =2V for the 21 bit, and
Vout =1V for the 20 bit (LSB).
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Successive - approximation ADC (4)…
Illustration of Basic operation with an example
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Successive - approximation ADC (5)…
Illustration of Basic operation with an example
• Step 1:
23 bit (MSB) = 1
The output of the DAC is 8 V.
Since this is greater than the input of 5.1 V, the output of
the comparator is LOW, causing the MSB in the
Successive Approximation Register (SAR) to be reset to
a0
• Step 2:
22 bit =1
The output of the DAC is 4 V.
Since this is less than the input of 5.1 V, the output of
the comparator switches to HIGH, causing this bit
retained in SAR.
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Successive - approximation ADC (6)
Illustration of Basic operation with an example
• Step 3:
21 bit = 1
The output of the DAC is 6 V.
Since this is greater than the input of 5.1 V, the output of the comparator
switches to LOW, causing this bit to be reset to 0.
• Step 4:
20 bit =1
The output of the DAC is 5 V.
Since this is less than the input of 5.1 V, the output of the comparator switches
to HIGH, causing this bit retained in SAR.
After 4 steps, conversion cycle is completed. Binary code in the register is
0101, which is approximately the binary value of the input of 5.1 V.
Vout=8V for the 23 bit (MSB),
Vout =4V for the 22 bit,
Vout =2V for the 21 bit, and
Vout =1V for the 20 bit (LSB).
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SIGMA - DELTA ADC (1)…
•
This method is based on delta modulation where the
difference between two successive samples is quantized.
•
The output of a delta modulator is a single bit data stream
where the relative number of 1’s and 0’s indicates the level of
amplitude of the input signal. The number of 1’s over a given
number of clock cycles establishes the signal amplitude during
that interval.
•
A maximum number of 1’s correspond to maximum positive
input voltage. A number of 1’s equal to one - half the
maximum corresponds to an input voltage of 0.
•
No 1’s correspond to the maximum negative input voltage.
•
This is illustrated in a simplified way in fig 10.
•
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SIGMA - DELTA ADC (2)…
Figure 10 A simplified illustration of sigma-delta analog-to-digital conversion.
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SIGMA - DELTA ADC (3)…
Figure 11 Functional block diagram of a sigma-delta ADC.
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SIGMA - DELTA ADC (4)…
•
The basic block diagram in Fig 11 accomplishes the
conversion . The analog input signal and the analog
signal form the converted quantized bit stream form the
DAC in the feedback loop are applied to the summation
point .
•
The difference signal output of the sum is integrated
and the 1-bit ADC increases or decreases the number of
1’s depending on the difference signal. This action
attempts to keep the quantization signal that is fedback
equal to the incoming analog signal. The 1 bit quantizer
is essentially a comparator followed by a latch.
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SIGMA - DELTA ADC (5)
The single bit data stream is converted to as series of
binary codes .The counter counts 1’s in the quantized
data stream for successive intervals .The code in the
counter then represents the amplitude of the analog
input signal for each interval.
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Digital to Analog Conversion MethodsBinary – weighted - input DAC
(1)…
Fig 12 shows a 4-bit DAC with binary weighted inputs. .
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Binary – weighted - input DAC
(2)…
Each of the input resistors will either have current or
no current depending on the input voltage level.
•
If the input voltage is zero, the current is also zero.
If input voltage is high ,the amount of current depends
on the input resistor value and is different for each input
resistor.
•
•
Since there is practically no current into the op-amp
inverting
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(-) input, all of the input currents sum together and go
through Rf . Since the inverting input is at 0v,the drop
across Rf is equal to the output voltage ,so Vout = If Rf .
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Binary – weighted - input DAC
(3)
•
The values of the input resistors are chosen to be inversely
proportional to the binary weights of the corresponding input bits.
The lowest value resistor (R) corresponds to the highest binary
weighted input (23).
•
The other resistors are multiples of R (R, 2R, 4R and 8R) and
correspond to the binary weights of 22 , 21 , 20 .
•
Thus the output voltage is proportional to the sum of binary
weights because the sum of the input currents is through Rf .
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The R/2R Ladder DAC (1)…
R/2R Ladder DAC is shown in fig 13.
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The R/2R Ladder DAC (2)…
Assume that D3 input is high (+5 v) and the others are
low(0 V) .This condition represents the binary number
1000.
Essentially no current goes through the 2R equivalent
resistors because the inverting input is at virtual ground .
Thus all the current (I= 5V/2R) through R7 also goes
through Rf and the output voltage is -5V.The op-amp
keeps the inverting input near 0V because of negative
feedback. Thus all current goes through Rf rather than
into the inverting input.
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The R/2R Ladder DAC (3)…
Fig 14
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The R/2R Ladder DAC (4)
Fig 14 (b) shows the equivalent circuit when the D2 input
at +5V and the others are grounded. This condition
represents 0100 , i.e.2.5V in series with R. This results
in a current through Rf of I = 2.5V/2R , which gives an
output voltage of -2.5V.
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Performance characteristics of DAC (1)…
1. Resolution : The resolution of a DAC is the reciprocal
of the number of discrete steps in the output .
For example a 4-bit DAC has a resolution of one part
in
24 -1 = 1/15*100 = 6.67%.
2. Accuracy: Accuracy is derived from a comparison of
the actual output of a DAC with the expected output.
It is expressed as a percentage of a full-scale or
maximum output voltage. If a converter has a fullscale output of 10v and the accuracy is +/- 0.1% ,then
the maximum error for any output voltage is
(10V)(0.001) = 10 mV
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Performance characteristics of DAC (2)…
Linearity: A linear error is a deviation from the ideal
straight-line output of a DAC.A special case is an offset
error. which is the amount of output voltage when the
input bits are all 0’s.
4. Monotonicity: A DAC is monotonic if it doesn’t take
any reverse steps when it is sequenced over its entire
range of input bits.
5. Settling Time: Normally defined as the time it takes a
DAC to settle within +/- ½ LSB of its final value when a
change occurs in the input code.
3.
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Performance characteristics of DAC (3)
• Example: Determine the resolution, expressed as a
percentage, of the following:
a. an 8-bit DAC
b. a 12-bit DAC
Solution:
a. For the 8-bit DAC,
1/28-1 *100 = 1/255*100=0.392%
b. For the 12-bit DAC,
1/212-1 *100 = 1/4095*100=0.0244%
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Real World Example
•A modem
(converts digital signals into analog signals for transmissions
over phone lines and the back to digital signals again at the
destination computer)
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