Transcript PLL with VCO Band Selection Ko

PLL
with VCO Band Selection
Ko-Chi Kuo
Auto Band Selection Outline
PART I: Concept Review


Auto Band Selection Concept
Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )
PART II: Circuit Design Review







Divide 8 and ECL to CMOS Circuit and Simulation
9 Bit Programmable Counter and Simulation
Band Selection Interface Schematic and Simulation
Reset DFF Schematic and Simulation
VCO Phase Noise Simulation
Auto Band Selection Simulation
Summary
PART I:Band Selection Concept Review
PART I: Concept Review


Auto Band Selection Concept
Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )
Auto Band Selection Concept











The need of Auto Band Selection
Multi-Band Solution Using CMOS Binary Digital Varactor
Frequency Coverage of RFVCO over 8 Bands
Requirements for Band Selection Algorithm to Work
How the Band Selection Works
Frequency Comparison Concept
Frequency Resolution with 8 Band RF VCO
Frequency Resolution with 4 Band IF VCO
Band Select Circuit Design
Band Select Circuit Timing Diagram
Summary
The need of Auto Band Selection
VCO frequency variations over temperature(2%) and
process(%9)
The minimum RF VCO Frequency Coverage(at RF LO)

2.xxGHz
2.36GHz
60MHz: Minimum required coverage for WCDMA
at any temperature
2.30GHz
2.yyGHz
Multi-band Solution Using CMOS Binary
Digital Varactor

Frequency Tuning is achieved through:


CMOS Binary Band-Select Capacitors
Small Integrated PIN Diode Varactor
Frequency
Total Frequency Coverage
at given process and temp.
Vtune
Frequency Coverage of RF VCO
over 8 Bands
Desired Cover Range 4.6 –4.72 GHz (2.56%)
Guard bands for process & temperature 5.4% each
Band overage is 84%. The band coverage at (000) is 230 MHz for Core VCO, 115MHz after divide-by-2.
* courtesy from Dawn Wang’s RFVCO CDR presentation.
Requirements for Band Selection
Algorithm to Work
1.
2.
Band Selection is performed each time a new channel is selected.
There is minimum overlap (f ) between two adjacent bands to cover the
maximum expected temperature drift (+/-100 degree C) once a band is
chosen.
.
.
.
.
Frequency
(LO)
.
.
.
.
.
Band=3
Band=2
Given Minimum Band Overlap (f) : 105MHz
1.
2.
3.
4.
100degree (C) temperature drift: +/- 40MHz
BS Algorithm tolerance: +/- 4MHz
Overlap: f
Vtune Bias Error: +/- 5MHz
Band separation Mismatch: This is accounted
for in the Minimum Band Overlap (f)

f > 2 x (40M + 4M + 5M) = 98MHz
Band=1
Band=0
0.5
2.35
Vtune
Band Switching Decision Point
How the Band Selection Works
1.
2.
3.
4.
5.
6.
At Power Up:
-- All registers set to zero (as default)
-- Vtune is set to 2.35V
Load (fLO (MHz) + 49) / 8 into Band
Select Register thru Serial Interface.
-- This loading action triggers Band
Select Algorithm
Compare Frequencies.
-- (fLO + 49MHz) / 8 > fVCO ?
Band selection counter (register)
counts up as long as (fLO + 49MHz) / 8
> fVCO .
Freeze BS Counter when:
(fLO + 49MHz) / 8 < fVCO
Vtune voltage control is released.
.
.
.
Frequency
(LO)
.
.
.
.
.
.
Band=3
Band=2
Band=1
Band=0
Overlap: f
0.5
2.35
Vtune
Band Switching Decision Point
* Above procedures are automatic except
steps 1 and 2.
•Comparison at 2.35Volts reduces algorithm
error caused by Vtune voltage variations
and Overlap variations.
ABS Interconnection Diagram & Operation
Synthesizer
RF_ABS
3bits
BS<2:0>
fREF
fREF _Off
Vtune
BS_Man
BS_Reset
EN( BS Enable)
Vtune
RBS<8:0>
2.35V
RF_VCO
9bits
VCO_in
•
•
•
R-register of IF PLL is used to generate 1MHz f_REF for both RF and IF ABS circuits.
BS_Man overrides ABS algorithm and allows manual control of Band_Sel <2:0>
BS_Reset resets all the registers inside ABS circuit blocks.
Start /
Power Up
ABS Operation Flowchart
Start Down Count
As default:
fREF = disabled
Freeze = Low (Disabled)
BS_Reset = Low
BS_Man = Low
Vtune = 2.35 Volts
Down Counter
reaches ‘0’ before
next fREF ?
Load R-Register of IF PLL
thru SI to output 1MHz
Load [ fLO(MHz) + 49] / 8 to
RBS & IBS thru S.I.
fLO is desired
VCO frequency
for IF and RF
PLL
Ready for normal
operation of PLL
• Reset BS <2:0> to zero
• fREF is enabled
Load RBS (or IBS) value
onto DN_Counter
• Freeze goes High
• fREF = Disable
• Freeze BS<2:0>
• Reset all other Reg’s to ‘0’
• Vtune_Release goes High
Vtune (VCO input) is
reconnected to loop filter
output for normal operation
Loading RBS & IBS tirggers
EN high – triggers BS
operation
Cnt_Start enabled at fREF
• Increase BS<2:0> by one
• Reload DN_Counter
yes
From here on
operation is
synchronized to
fREF
END
Frequency Resolution with
8 Band RF VCO
2.35V
freq
(GHz)
8/freq
(nS)
297*8/freq
(S)
Band0
2.28
3.51
1.042
Band1
2.31
3.46
1.028
Band2
2.34
3.42
1.015
Band3
2.38
3.37
1.002
Band4
2.40
3.33
0.988
Band5
2.44
3.29
0.976
Band6
2.47
3.25
0.964
Band7
2.49
3.21
0.952
Vtune
Band
1.
The resolution of band selection
counter is set to (fLO + 49MHz) / 8 so
that difference between two band can
be larger enough to chose the right
band. In this case, each difference is
about 3~4 clock cycles.
Frequency Resolution with
4 Band IF VCO
2.35V
Vtune
Band
freq
(GHz
)
Band0
1.50 5.33 1.040
Band1
1.53 5.23 1.020
Band2
1.58 5.06 0.987
Band3
1.65 4.85 0.945
1.
8/fre
q
(nS)
195*8/fre
q
(S)
Given Minimum Band Overlap (f) : 82MHz
1.
100degree (C) temperature drift: +/- 26MHz
2.
BS Algorithm tolerance: +/- 4MHz
3.
Vtune Bias Error: +/- 4MHz
4.
Band separation Mismatch: This is accounted
for in the Minimum Band Overlap (f)

f > 2 x (26M + 4M + 4M) = 68MHz
The resolution of band selection
counter is set to (fLO + 34MHz) / 8 so
that difference between two band can
be larger enough to chose the right
band. In this case, each difference is
about 4~8 clock cycles.
Band Selection Circuit Design(RF)
2330MHz / 8 = 291MHz
Vtune
9-bits
fVCO / 8
VCO
8
9-bit
Down Cntr
DN_Cnt
Vtune_Release
Band_Sel<2:0>
Freeze
D Q
FREF
RMB
Freeze
D Q
Freeze_b
EN
Band_Sel <2:0>
BSR
D Q
CNT_Start
Reload
BS_Cnt
Q
fREF
D Q Reload
fREF
D Q
Q
Q
DN_Cnt
rst
BSR
3-bit
Counter
3-bit
rst
rst
Freeze
Q
EN
Decode_C
TWIF_ENB
D Q
EN
Freeze
D Q
BS_enable
Freeze
Q
Cntr = high ?
Reload
fVCO / 8
BS_enable
Load (fLO (MHz) + 49) / 8 every 1sec
using : RBS register
rst
TWIF_Clk
TWIF_ENB
RMB
BS_Man
2.35V
LPF_out SWITCH
* Using Clk and En inputs of S.I.
to manually control Band Selection
* BSR, RBS and RMB are inputs from S.I.
* Vtune is determined by vtune release
LPF_out is from off-chip LPF
EN
BSR
Freeze
RMB
Vtune_Release
Vtune
Band Selection Circuit Design(IF)
1554MHz / 8 =194MHz
Vtune
8-bits
fVCO / 8
VCO
8
DN_Cnt
9-bit
Down Cntr
Vtune_Release
Band_Sel<2:0>
Freeze
D Q
FREF
RMB
Freeze
D Q
Decode_C
TWIF_ENB
Band_Sel <1:0>
D Q
CNT_Start
Reload
BS_Cnt
Q
fREF
rst
D Q
Reload
D Q
Q
BSR
rst
* Using Clk and En inputs of S.I.
to manually control Band Selection
* BSR, RBS and IMB are inputs from S.I.
* Vtune is determined by vtune release
LPF_out is from off-chip LPF
3-bit
Counter
3-bit
rst
Q
DN_Cnt
EN
BSR
rst
Freeze
Q
EN
Freeze
fREF
D Q
Freeze_b
EN
BSR
D Q
BS_enable
Freeze
EN
Q
Cntr = high ?
Reload
fVCO / 8
BS_enable
Load (fLO (MHz) + 34) / 8 every 1sec
using : RBS register
TWIF_Clk
TWIF_ENB
IMB
BS_Man
2.35V
LPF_out SWITCH
Freeze
IMB
Vtune_Release
Vtune
Band Selection Circuit Timing Diagram
fREF
EN
BS_Enable
Freeze
Cnt_Start
Reload
Dn_Cnt
BS_Cnt
Summary of Auto Band Selection Algorithm




Band Selection is necessary for the RF and IF VCOs
in order to overcome the VCO frequency drift due to
the process and temperature variations.
The proposed Band Selection Algorithm takes 2sec
per band and less than 20 sec(RF)/12 sec(IF) to
accomplish Automatic Band Selection.
Frequency comparison is made through counting the
frequency of fRF/8 signal during 1sec (all digital
solution.)
Small overhead in silicon area and No Extra Current
Consumption.
PART I:Band Selection Concept Review
PART I: Concept Review


Auto Band Selection Concept
Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )
Auto Band Selection Interface with
other Blocks(PLL, VCO, LPF, S.I.)


RF Top Schematic of ABS, PLL, VCO, LPF, and S.I.
IF Top Schematic of ABS, PLL, VCO, LPF, and S.I.
RF TOP of ABS, PLL, VCO, LPF, S.I.
RPC<8:0>
RSC<4:0>
RRC<7:0>
CPS<1:0>
Data
TWIF_Clk
TWIF_EN
Serial Interface
RPE
RCP
TCXO
Iout
RF PLL
Oscillator
RF
LPF_out
Low Pass Filter
FREF
(From IF
PLL)
SWITCH 2.35V
vcon_rf
vcop_rf
RF VCO
Vtune
Vtune_release
RF
Auto Band Selection
Band_Sel<2:0>
RVE
RBS<8:0>
BSR
RMB
Decode_C
IF TOP of ABS, PLL, VCO, LPF, S.I.
IPC<8:0>
TCXO
Oscillator
IRC<7:0>
CPS<1:0>
Data
TWIF_Clk
TWIF_EN
Serial Interface
IPE
ICP
Iout
IF PLL
IF
Low Pass Filter
LPF_out
FREF
(From IF
PLL)
SWITCH 2.35V
vcon_if
vcop_if
IF VCO
Vtune
Vtune_release
IF
Auto Band Selection
Band_Sel<1:0>
IVE
IBS<7:0>
BSR
IMB
Decode_C
PART II:Band Selection
Circuit Design Review
PART II: Circuit Design Review








Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation
9 Bit Programmable Counter Schematic and Simulation
Band Selection Interface Schematic and Simulation
Reset DFF Schematic and Simulation
VCO Phase Noise Simulation
Auto Band Selection Top Level Simulation
ABS, PLL, VCO, LPF Top Level Simulation
Summary
Auto Band Selection: Divide 8, Biasing, CML
to CMOS Circuits




Auto Band Selection: Divide 8, Biasing
Corner Simulation Condition
Circuit Simulation Result
Simulation Summary
Auto Band Selection: Divide 8 and Biasing
RBS<8:0> (from S.I.)
VCO_vtune
(to VCO vtune)
Control Signal
(from S.I.)
Vtune_release
LPF_out
(from LPF)
Band Selection
Auto Band
Interface
8
PWD
Vbias
Bias
circuit
Control
Logic
FREF
(From IF PLL)
Band_Sel<2:0>
9-bit
Down Cntr
3-bit
Counter
(to VCO Band select lines)
Vtune_release
Reset
Power on
Reset circuit
Auto Band Selection Divide 8 and
CML to CMOS circuit Simulation Corner
Process: bipolar fast(3), resistor fast(3), temp =-20C
Process: bipolar fast(3), resistor slow(-3), temp =-20C
Process: bipolar slow(-3), resistor fast(3), temp =-20C
Process: bipolar slow(-3), resistor slow(-3), temp =-20C
Process: bipolar fast(3), resistor fast(3), temp =85C
Process: bipolar fast(3), resistor slow(-3), temp =85C
Process: bipolar slow(-3), resistor fast(3), temp =85C
Process: bipolar slow(-3), resistor slow(-3), temp =85C
Frequency is set at 2.5GHz, Supply Voltage is 2.85V
Auto Band Selection: Divide 8 and CML to
CMOS circuit Simulation Result
Freq=2.5G Supply=
2.85V
(1/freq/8)
current
Design_bfrf, -20C
3.2n
2.147mA
Design_bfrs, -20C
3.2n
3.296mA
Design_bsrf,-20C
3.2n
2.179mA
Design_bsrs, -20C
3.2n
3.324mA
Design_bfrf, 85C
3.2n
2.122mA
Design_bfrs, 85C
3.2n
3.285mA
Design_bsrf, 85C
3.2n
2.258mA
Design_bsrs, 85C
3.2n
3.488mA
Auto Band Selection Divide 8 and
CML to CMOS circuit
Simulation Summary
Minimu
m
Typic
al
Maximu
m
Units
Power Supply
2.85
3
3.15
V
[email protected]
2.122
3.488
mA
2.5
GHz
Operating
Frequency
2.36
PART II: Circuit Design Review








Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation
9 Bit Programmable Counter Schematic and Simulation
Band Selection Interface Schematic and Simulation
Reset DFF Schematic and Simulation
VCO Phase Noise Simulation
Auto Band Selection Top Level Simulation
ABS, PLL, VCO, LPF Top Level Simulation
Summary
Auto Band Selection: 9 Bit Programmable
Counter






Auto Band Selection: 9 Bit Programmable Counter
Corner Simulation Condition
Circuit Simulation Result
Power down/up Simulation Result
Corner Simulation Result
Simulation Summary
Auto Band Selection: 9 Bit Programmable
Counter
RBS<8:0> (from S.I.)
VCO_vtune
(to VCO vtune)
Control Signal
(from S.I.)
Vtune_release
LPF_out
(from LPF)
Band Selection
Auto Band
Interface
8
PWD
Vbias
Bias
circuit
Control
Logic
FREF
(From IF PLL)
Band_Sel<2:0>
9-bit
Down Cntr
3-bit
Counter
(to VCO Band select lines)
Vtune_release
Reset
Power on
Reset circuit
Auto Band Selection Circuit Design
9 Bit Programmable Counter
Simulation Corner
Process: nfet fast(3), pfet fast(3), temp =-20C
Process: nfet fast(3), pfet slow(-3), temp =-20C
Process: nfet slow(-3), pfet fast(3), temp =-20C
Process: nfet slow(-3), pfet slow(-3), temp =-20C
Process: nfet fast(3), pfet fast(3), temp =85C
Process: nfet fast(3), pfet slow(-3), temp =85C
Process: nfet slow(-3), pfet fast(3), temp =85C
Process: nfet slow(-3), pfet slow(-3), temp =85C
Frequency is set at 2.5GHz, Supply Voltage is 2.85V
Auto Band Selection 9 Bits Counter
Corner Simulation Results
Freq=2.5G,
Supply=2.85
1/(freq/8)/312)
current
Design_nfpf, -20C
998.397nS
1.052mA
Design_nfps, -20C
998.397nS
1.227mA
Design_nspf,-20C
998.397nS
1.389mA
Design_nsps, -20C
998.397nS
1.593mA
Design_nfpf, 85C
998.397nS
1.12mA
Design_nfps, 85C
998.397nS
1.31mA
Design_nspf, 85C
998.397nS
1.478mA
Design_nsps, 85C
998.397nS
1.678mA
Auto Band Selection 9 Bits Counter
Simulation Summary
Minimu
m
Typical
Maxim Units
um
Power Supply
2.85
3
3.15
V
[email protected]
1.052
1.678
mA
Division
2
298~30
8
512
Count
s
2.36
2.5
GHz
Operating
Frequency
PART II: Circuit Design Review








Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation
9 Bit Programmable Counter Schematic and Simulation
Band Selection Interface Schematic and Simulation
Reset DFF Schematic and Simulation
VCO Phase Noise Simulation
Auto Band Selection Top Level Simulation
ABS, PLL, VCO, LPF Top Level Simulation
Summary
Auto Band Selection: Band Selection
Interface





Auto Band Selection: Band Selection Interface
Auto Band Selection: Band Selection Interface Buffer Circuit worst case
simulation
Auto Band Selection: Band Selection Interface Circuit Simulation Result
Auto Band Selection: Band Selection Interface with VCO, PLL, LPF
Simulation Result
Simulation Summary
Auto Band Selection: Reference Clock
Generator
RBS<8:0> (from S.I.)
VCO_vtune
(to VCO vtune)
Control Signal
(from S.I.)
Vtune_release
LPF_out
(from LPF)
Band Selection
Auto Band
Interface
PWD
Bias
circuit
8
Vbias
Control
Logic
FREF
(From IF PLL)
Band_Sel<2:0>
9-bit
Down Cntr
3-bit
Counter
(to VCO Band select lines)
Vtune_release
Reset
Power on
Reset circuit
Auto Band Selection Band Selection
Buffer Worst Case Simulation
Simulation case Simulation parameter
:Temp, supply voltage,
MOS corner model
AC worst case: 85C, 2.85V supply,
Smallest PM
PMOS=3, NMOS=-3
(open loop )
Transient case:
largest delay
85C, 2.85V supply,
PMOS=-3, NMOS=-3
Auto Band Selection Interface:Buffer
AC Phase Margin Simulation
AC open loop gain=70dB
Phase Margin=60
Auto Band Selection Interface:Buffer
Step Input Response Simulation
vout
Step input
Settling time=200ns
Auto Band Selection Interface
Simulation Result
VCO_Vtune
(goes to VCO)
PWD
(generated by
this interface)
Vtune_release
Power_down
LPF_in
(comes from LPF)
VCO_Vtune=2.35V
(settled 300ns after power on)
This is power
on period
VCO_Vtune=LPF_in
(after ABS find the right band)
ABS find the right
band and shut
down the ABS
Auto Band Selection Interface with VCO,
PLL, LPF Simulation Result
LPF initial condition :0.5V
VCO_Vtune
Vtune_release
Auto Band Selection Interface with VCO,
PLL, LPF Simulation Result
LPF initial condition :2.35V
VCO_Vtune
Vtune_release
Auto Band Selection Interface
Simulation Summary



The Interface circuit provides the VCO vtune voltage
based on ABS status, one is a fixed 2.35V, the other
source is from off-chip LPF output.
When ABS select the right band, it generates the
power down signal to shut down the current of ABS
circuit.
Simulation result shows that after interface circuit
shut down ABS, PLL and VCO can still handle LPF
initial condition.
PART II: Circuit Design Review








Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation
9 Bit Programmable Counter Schematic and Simulation
Selection Interface Schematic and Simulation
Band Reset DFF Schematic and Simulation
VCO Phase Noise Simulation
Auto Band Selection Top Level Simulation
ABS, PLL, VCO, LPF Top Level Simulation
Summary
Auto Band Selection: Band Power On Reset
DFF Circuit


Auto Band Selection: Band Power On Reset DFF Circuit
Circuit Simulation Result
Auto Band Selection: Band Power On Reset
DFF Circuit
RBS<8:0> (from S.I.)
VCO_vtune
(to VCO vtune)
Control Signal
(from S.I.)
Vtune_release
LPF_out
(from LPF)
Band Selection
Auto Band
Interface
PWD
Bias
circuit
8
Vbias
Control
Logic
FREF
(From IF PLL)
Band_Sel<2:0>
9-bit
Down Cntr
3-bit
Counter
(to VCO Band select lines)
Vtune_release
Reset
Power on
Reset circuit
Auto Band Selection Reset DFF
Simulation Result
Power On
Reset
Power On
PART II: Circuit Design Review








Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation
9 Bit Programmable Counter Schematic and Simulation
Selection Interface Schematic and Simulation
Band Reset DFF Schematic and Simulation
VCO Phase Noise Simulation
Auto Band Selection Top Level Simulation
ABS, PLL, VCO, LPF Top Level Simulation
Summary
Auto Band Selection: VCO and Switch Phase
Noise Test




Circuit Simulation Result
Auto Band Selection: VCO and Switch (with divide 2) Phase Noise Test
Bench
Circuit Simulation Result
Simulation Summary
Auto Band Selection: VCO and Switch Phase
Noise Test



Circuit Simulation Result
Circuit Simulation Result
Simulation Summary
Auto Band Selection :VCO Simulation Result
VCO with Switch
-120.04dBc/Hz@1MHz
VCO without Switch
-120.252dBc/Hz@1MHz
Auto Band Selection
VCO and Switch
Simulation Summary



Auto Band Selection: VCO and Switch Phase Noise Test Bench
Simulation result shows no degradation between VCO with switch and
VCO without switch.
Auto Band Selection: VCO and Switch(with Divide 2) Phase Noise Test
Bench Simulation result shows 0.15dBc/Hz@1MHz degradation
between VCO with switch and VCO without switch.
Auto Band Selection: VCO and Switch(with Divide 2) PSS Simulation
result shows 0.15dBc/Hz@1MHz degradation between VCO with
switch and VCO without switch
Auto Band Selection
VCO and Switch
Simulation Summary



Auto Band Selection: VCO and Switch Phase Noise Test Bench
Simulation result shows no degradation between VCO with switch and
VCO without switch.
Auto Band Selection: VCO and Switch(with Divide 2) Phase Noise Test
Bench Simulation result shows 0.15dBc/Hz@1MHz degradation
between VCO with switch and VCO without switch.
Auto Band Selection: VCO and Switch(with Divide 2) PSS Simulation
result shows 0.15dBc/Hz@1MHz degradation between VCO with
switch and VCO without switch
Auto Band Selection
VCO and Switch
Simulation Summary



Auto Band Selection: VCO and Switch Phase Noise Test Bench
Simulation result shows no degradation between VCO with switch and
VCO without switch.
Auto Band Selection: VCO and Switch(with Divide 2) Phase Noise Test
Bench Simulation result shows 0.15dBc/Hz@1MHz degradation
between VCO with switch and VCO without switch.
Auto Band Selection: VCO and Switch(with Divide 2) PSS Simulation
result shows 0.15dBc/Hz@1MHz degradation between VCO with
switch and VCO without switch
Auto Band Selection Top Level Simulation
RPC<8:0>
RSC<4:0>
RRC<7:0>
CPS<1:0>
Data
TWIF_Clk
TWIF_EN
Serial Interface
RPE
RCP
TCXO
Iout
RF PLL
Oscillator
RF
Low Pass Filter
LPF_out
FREF
(From IF
PLL)
SWITCH 2.35V
vcon_rf
vcop_rf
RF VCO
Vtune
Vtune_release
Band_Sel<2:0>
RVE
RF
Auto Band
Selection
RBS<8:0>
BSR
RMB
Decode_C
ABS Top Level Simulation Result
Band 7 is selected
BS0
BS1
BS2
Vtune_Release
CNT_Start
DN_CNT
BS_Cnt
ABS Top Level Simulation Result
Band 7 is selected
BS0
BS1
BS2
Vtune_Release
CNT_Start
DN_CNT
BS_Cnt
ABS, PLL, LPF, VCO
Top Level Simulation
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ABS, PLL, LPF, VCO : Top Level Simulation
Circuit Simulation Result
ABS, PLL, LPF, VCO, S.I Top Level Schematic and List of
interconnection
ABS, PLL, LPF, VCO
Top Level Simulation
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ABS, PLL, LPF, VCO : Top Level Simulation
Circuit Simulation Result
ABS, PLL, LPF, VCO, S.I Top Level Schematic and List of
interconnection
ABS, PLL, LPF, VCO Top Level VerilogA
Model Simulation Result
Vtune_release
LPF_in
CP_out
PLL start normal function
PLL settle
PART II: Circuit Design Review
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Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation
9 Bit Programmable Counter Schematic and Simulation
Reference Clock Schematic and Simulation
Selection Interface Schematic and Simulation
Band Reset DFF Schematic and Simulation
VCO Phase Noise Simulation
Auto Band Selection Top Level Simulation
ABS, PLL, VCO, LPF Top Level Simulation
Summary
Auto Band Selection Circuit
Simulation Summary
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Band Selection Circuit start chose band 2S after EN signal
enabled and takes additional up to 16S to chose the right band
for VCO. The total selection time is 18S(RF), 10S(IF).
The Power Up takes 1S which is smaller than 2S.
Whenever channel changed, both RF and IF ABS will be
enabled to select the right band again.
Band Selection Circuit will shut down when the right band is
selected.
The simulation of VerilogA model: PLL,VCO, ABS, LPF shows
that ABS can work properly with other related blocks.
The phase noise of VCO has 0.15dBc/Hz @ 1MHz degradation
by adding additional switch on the vtune line.