Transcript Dispositivi Logici Programmabili

Novel,
Emerging
Computing System Technologies
DIPARTIMENTO DI ELETTRONICA E INFORMAZIONE
Smart Technologies
for Effective Reconfiguration:
The FASTER approach
May 29th – 31st 2013
International Conference on IC Design and Technology
Pavia, Italy
M. D. Santambrogio, C. Pilato, D. Pnevmatikatos,
K. Papadimitriou, D. Stroobandt, D. Sciuto
http://www.fp7-faster.eu/
Reconfigurable Technology
• Technology for adaptable hardware systems
 Can add/remove components at run-time/product
lifetime
 Flexibility at hardware speed (not quite ASIC)
 Parallelism at hardware level (depending on
application)
 Ideally: alter function & interconnection of blocks
• Implementation in:
 FPGAs: fine grain, complex gate plus memory and
DSP blocks
 Coarse Grain (custom) chips: multiple ALUs, multiple
(simple) programmable processing blocks, etc.
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An issue as a new opportunity
• Programming has become very difficult
 Impossible to balance all constraints manually
• More computational horse-power than ever before
 Cores are free, reconfigurable logic available on chip, cores
can be heterogeneous
• Energy is new constraint
 Software must become energy and space aware
• Modern computing systems need to be flexible and
adaptive
 To optimize and meet their requirements taking
advantage as much as possible of the underlying
complex heterogeneous architectures
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FASTER Motivation
• Creating reconfigurable systems is not
straightforward!
 Reconfiguration cost is substantial (use wisely)
 Tool support for these tasks is still quite basic
 Resource management is up to the user
 The designer has to:
 Identify portions to be reconfigured
 Establish a schedule that (a) respects dependencies
(b) achieves performance and other constraints
 Manage the system resources (also at run-time)
 Verify a changing system!
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FASTER Goals and Innovation
• Include reconfigurability as an explicit design
concept in computing systems design, along
with methods and tools that support run-time
reconfiguration in the entire design
methodology
 Provide a framework for analysis, synthesis and
verification of a reconfigurable system
 Provide efficient and transparent runtime support
for partial and dynamic reconfiguration, including
micro-reconfiguration
• Demonstrate usability & performance on
commercial applications and platforms
(Maxeler, ST Microelectronics, Synelixis)
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FASTER Platforms
• Bridging the gap between HPC and embedded
systems
 Opportunities and challenges of reconfiguration in
both the domains
• High-Performance Computing Systems
 Maxeler MPC MaxWorkstation
• FPGA-based Embedded Systems
 Xilinx University Program Board (XUPV5-LX110T)
 AVNET Zedboard (SoC XC7Z020)
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FASTER: Overall Methodology
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Design Phase and Runtime Support
WP3 (back-end)
List of HDL func ons
+
C descrip on
+
Parallelism
annota ons
(openMP)
XML descrip on
- App
- Pla orm
- HW/SW par oning
App Designers
Library w/ SW/HW I/F
modules
WP2 (front-end)
Sta c
High-level analysis.
Contains rough/fast
es ma on of
a)Power,
b)Resources,
i
c)Computa on me
Iden fica on of
PR cores +
Applica on
profilng
Op miza on for
microreconfigura on
(TLUT, TCON)
(iden fy annota ons
needed on C/HDL)
Reference
design
Vendor-flow
Reuse
Baseline
scheduling +
Floorplanning
Region-based
Micro-reconfig.
Vendor-flow +
relocation
UGent +
Vendor-flow
Static Area
Reconfigurable Area
System
GPP
RR2
RR1
SW
Verification
Param.
change
RTSM
SW
tools
WP4 (runtime)
•
Define a reconfiguration-aware design methodology that exploits FPGAs:

•
Exploit dynamic reconfigurability for different target reconfigurable architectures.

•
Generate hardware and software components (including runtime support) on the top of
existing vendor flows
Both HPC and embedded systems
Define and implement a new generation of self reconfigurable architectures
based on Linux
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System analysis and design
.c
- Annotated source code
(C+OpenMP)
Task Graph
Generation
.xml
- Architecture
- Additional application information
DFG Extraction
.xml
Partitioning
and Optimizations
Run-time Support
and Verification
.c
High Level Analysis
Static Baseline
Scheduling
- Source code for CPU
Mapping and
Floorplanning
.xml
- DFGs for HW blocks
- Mapping Configurations
- HLS
- System generation
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Identifying Level of Reconfigurability
• Assigning each task of the application to the
“best” processing element
 Reconfiguration is implicitly considered
• Based on a metaheuristic iterative algorithm
Architectural
Template
XML
T1
T2
T3
Objectives: function of occupation area,
execution time, power, number of
reconfigurations etc...
MAP
T4
T5
Library
XML
Convergence
Mapping
Iterative, multi objectives:
-Runtime
-Power
-Area
-…
Platform
Specification
XML
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Micro-reconfiguration Optimization
• In some applications we can identify hardware
accelerators with slow‐changing “parameters”
 Filter coefficients
• Parameters trigger a small-scale reconfiguration
• Design of cores based on Tunable FPGA blocks:
 Identify parameters
 Create bitfile with “holes”
 Parameter values => reconfiguration bits for
missing “holes”
 Fine grain, faster reconfiguration time!
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Verifying Reconfigurable Systems
• Study design validation approaches: simulation,
emulation and formal verification
• Extend symbolic simulation to dynamic aspects
of reconfigurable design
• In some cases static approaches may not be
able to verify the entire RC system
 We use run‐time verification. Address and minimize
impact on:
• Speed, area and power
• Light‐weight architectural support
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Run-time System
• Evaluate reconfiguration overhead
• Propose advanced mechanisms to support
 Scheduling
 Dynamic reconfiguration (including microreconfiguration)
 Run-time verification
• Provide run-time support for dynamic
reconfiguration based on static analysis
 Extension of OS capabilities
 Efficient on-line scheduling and placement of task
modules
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OS-based Management
• Provide software support for dynamic partial
reconfiguration on a Linux-based operating
systems
 Reconfiguration process managed from the OS in
a transparent way
• Hardware-independent interface for software
developers based on the GNU/Linux
 Addition and removal of reconfigurable
components
• Easier programming interface for specific
drivers
 OS customization for specific architectures
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Expected Results and Conclusions
• FASTER is a focused project that builds on
combined partners expertise as well as on past
research work and projects
• We focus on (and hope to demonstrate):
 productivity improvement in implementation and
verification of dynamically changing systems
 total ownership cost reduction (NIDS and RTM
systems)
 performance improvement under power
constraints for Global Illumination and Image
Analysis application
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Challenges & Opportunities
• Tool support for analysis and system
definition
• Specification of changing system(s)
• Reconfigurable granularity: influenced
by tools and applications
• Architectural support for reconfiguration
(vendor?)
• Metrics: include design effort/time, total
ownership cost
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