Transcript Interrupts

Interrupts and Exception Handling
Execution
• We are quite aware of the Fetch, Execute
process of the control unit of the CPU
– Fetch and instruction as indicated by the contents of
the PC (PC can be incremented at the same time)
– Execute the instruction.
• External events cause a change in this flow
– I/O device ready
– Input done
• Internal events can cause a change in this flow
– Divide by 0
– Overflow
Detecting Interrupt
• Bad choices
– Spin Waiting
• Have a loop that checks for the event and waits
until it happens
– Checking periodically.
• Event may never happen
• Difficult to program to “catch” event.
• Want to keep I/O device working as much
as possible since it is slowest.
Interrupt processor
• Use a separate computer dedicated to
detecting and handling external events.
• But would need one for each device so
that won’t have problems with multiple
events.
• Now CPU only communicates with other
processors (fast) not with devices (slow).
Exception Mechanism
• Using multiple computers (one for each
device) is expensive.
• Allow the computer to execute more than
one program at a time.
– Of course cannot execute more than one
instruction at a time (with one cpu)
– Just looks like it because the cpu is switching
from one program to another very quickly.
Exception Handling
• When an exception occurs, the state of the
cpu must be saved.
– Save registers (including PC)
• Jump to the section of code to handle the
interrupt (the exception handler).
• Restore the state of the cpu before
returning back to original program.
Components
• An interrupt is a change of the normal flow
of a program.
• The hardware must determine when to
interrupt the cpu and transfer program
control to the exception handler (software).
• Since the exception handler can be called
at any time, there cannot be any
arguments passed or return value.
Operating System
• The operating system controls and
allocates the use of all system resources,
such as, the cpu, memory, I/O devices, etc
• This allocation is coordinated by
interrupting running programs to handle
asynchronous I/O requests.
• This allows multiple independent programs
to share the computer (multiprogramming)
Efficiency
• When a program needs some input (from
keyboard, disk, etc.) it will take a significant
amount of cpu time to complete
• Rather than sitting idle, the cpu can work on
another task.
• Allows for time sharing
– Each process gets some time slice of cpu time.
– Interrupt occurs at the end of the time slice
– Operating system can switch to another process
Program Status
• Running – process is on the cpu and
executing
• Blocked – process is waiting for an I/O
request to complete
• Ready – No longer blocked, awaiting to
become running
• A change in status occurs via an interrupt
Kernel
• The kernel is the part of the operating
system that handles interrupts.
• There must be some instructions for the
operating system that cannot be used by
the user (such as access to I/O devices,
special purpose registers, etc.)
• The OS uses registers $26 and $27 for
servicing interrupts. Users can use them
but their values will change at
unpredictable times.
Types of Exceptions
• I/O
• Time slice complete – uses a hardware
timer.
• Extraordinary conditions during execution
– Divide by 0
– Overflow
– Illegal instruction or memory address
– This method is called a trap since generated
internally, not externally to the program
Terms
• An exception is either a trap or an interrupt
• Trap
– generated internal to the program
– synchronous
• Interrupt
– Generated external to the program
– Asynchronous
Processor Modes
• The MIPS processor has 2 modes
– Kernel
– User
• Kernel mode allows access to the kernel
registers (Not discussed yet) and the
upper half of memory.
• Interrupt handlers and other operating
system data is in the upper half of memory
• The operating system executes in kernel
mode
Co-processors
• Coprocessor C1 has the floating point
hardware.
– Without C1, floating point instructions cause
trap and the handler “fakes” the floating point
instruction with several integer instructions.
• TAL uses the instructions mtc1(move to
c1) and mfc1 (move from c1) to move data
between floating point and general
registers.
– Similarly with coprocessor 0 (mtc0, mfc0)
Coprocessor C0
• Accessible only in kernel mode.
• Register have special purposes.
– Status Register (12)
– Cause Registion (13)
– Exception Program Counter (14)
Cause Register
• Gives information about what caused an
exception.
– Bits 2-6 give a 5 bit value (0-32) about the
kind of exception
• Interrupt, load from illegal address, bus error on
fetch, bus error on data reference, syscall
instruction, break instruction, reserved instruction,
coprocessor unusable, arithmetic overflow, trap,
floating point.
– Bits 10-15 indicate external interrupt.
Status Register
• Bit 1 – kernel or user mode
• Bit 3 – mode when last interrupt occurred
• Many more
Exception Handler
• An exception is not invoked by a JAL, so
what about the return address?
• When an exception occurs, the processor
jumps to 0x80000080
• The Exception Program Counter register is
loaded with the address of the instruction
being executed when the interrupt
occurred.
• The interrupt handler can move this to a
general register and save it.