Transcript ECE 598 EP
Revisit CMOS Power Dissipation • Digital inverter: 2 P CLVDD f I leakVDD PSC – Active (dynamic) power – Leakage power – Short-circuit power (ignored) P N VDD CL Roy & Prasad (2000) © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 1 Leakage vs. Active Power Trends W. Haensch, IBM J. Res. Dev. 50, 339 (2006) I leak VGS Vth W 2 eff COX m 1VT exp Leff mVT © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips VDS 1 exp VT 2 Some Observations with Leakage I leak VGS Vth W 2 eff COX m 1VT exp Leff mVT VDS 1 exp VT • This is the “usual” (BSIM, Spice) leakage model • The thermal voltage VT = kBT/q • This model was derived for 3-dimensional carrier motion, impinging on a small energy barrier (what about 1-D or 2-D transistors?) • This model assumes some average “junction temperature” T but T itself is unsteady during digital operation! (what about hot phonons?!) © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 3 What About Energy? • Energy is a better metric when worried about battery life • So look at energy, not power minimization: • Critical difference: leakage energy depends on circuit delay, tp VDD 1 CLVDD ? Delay 1.3 f I Dsat (VDD Vth ) 2 Power fVDD © 2010 Eric Pop, UIUC 2 Energy VDD ECE 598EP: Hot Chips 4 Effects of Lowering VDD B. Zhai, IEEE Trans. VLSI Sys. 13, 1239 (2005) • Easy observation: lowering VDD lowers power and energy… the latter up to a point! • How low VDD? • It is theoretically possible to operate circuits near VDD ~ 50 mV, deep into the subthreshold regime! • So… why not do it? © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 5 Energy-Voltage Trade-Off B. Zhai, IEEE Trans. VLSI Sys. 13, 1239 (2005) • Remember, delay: CLVDD tp I ON • At high VDD ION = ID,sat • At low VDD delay too high, so leakage energy goes up as well 2 P CLVDD f I leakVDD 2 E CLVDD IleakVDDt p © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips Optimum VDD! 6 Principles of Low-Power Design Roy & Prasad (2000) • Use the lowest possible supply voltage (VDD) • Use the smallest geometry, highest frequency devices BUT operate them at the lowest possible frequency (f) • Use parallelism and pipelining to lower required frequency of operation • Manage power by disconnecting power source when system is idle (sleep states) • Design systems to have lowest requirements of performance for the given user functionality © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 7 Leakage Model: Closer Look I leak VGS Vth W 2 eff COX m 1VT exp Leff mVT VDS 1 exp VT • Strongly (exponentially!) temperature dependent! • Typically people use ΔT = PRTH where – ΔT is an average “junction temperature” – P is a time-averaged power dissipation (active + leakage) • How do we calculate RTH? • And when is it OK to use it? © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 8 Device Thermal Resistance Data Single-wall nanotube SWNT 100000 High thermal resistances: • SWNT due to small thermal conductance (very small d ~ 2 nm) RTH (K/mW) 10000 1000 100 • Others due to low thermal conductivity, decreasing dimensions, increased role of interfaces GST Phase-change Memory (PCM) Silicon-onInsulator FET SiO2 10 Cu Cu Via Power input also matters: 1 0.1 0.01 • SWNT ~ 0.01-0.1 mW Si 0.1 Bulk FET L (m) 1 • Others ~ 0.1-1 mW 10 Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006). © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 9 Modeling Device Thermal Response 100000 • Steady-state models RTH (K/mW) 10000 – Lumped: Mautry (1990), Goodson-Su (1994-5), Pop (2004), Darwish (2005) 1000 100 SOI FET 10 1 – Finite-Element 0.1 0.01 Bulk FET 0.1 L (m) 1 10 D L tSi W tBOX Bulk Si FET RTH 1 1 2kSi D 4kSi LW © 2010 Eric Pop, UIUC SOI FET RTH 1 2W 1/ 2 t BOX k BOX k Si tSi ECE 598EP: Hot Chips 10 Modeling Device Thermal Response • Transient Models – Lumped: Tenbroek (1997), Rinaldi (2001), Lin (2004) – Introduce CTH usually with approximate Green’s functions; heated volume is a function of time (Joy, 1970) Instantaneous T rise T E Pt C cV Due to very sharp heating pulse t ‹‹ V2/3/ – Finite-Element More general Simplest (~ bulk Si FET) P r T (r , t ) erfc 2 kSi r 2 t t r 2 1 P(t ') T (r , t ) exp dV ' dt ' 3/ 2 3/ 2 8 cV ( ) 0 (t t ') 4 (t t ') Temperature evolution anywhere (r,t) due to arbitrary heating function P(0<t’<t) inside volume V (dV’ V) (Joy 1970) Temperature evolution of a step-heated point source into silicon half-plane (Mautry 1990) © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 11 Approaches for Thermal Resistance Interconnect • Time scale: – Transient – Steady-State • Geometric complexity: – Lumped element (shape factors) Via + Interconnect – Analytic – Finite element (Fourier law) D L tSi W tBOX Bulk Si FET © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips SOI FET 12 Shape Factors Sunderland, ASHRAE (1964), many others • Heat flux: q = Sk(T1-T0) • Equivalent thermal resistance RTH = 1/Sk © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 13 Ex: Heat Loss from Via + Interconnect Chen, Li, Rosenbaum, Kang, IEEE TCAD ICS 19, 197 (2000) Cu Estimating heat loss (thermal resistance) “looking into” one Cu line: SiO2 2r zTOP Th,eff AVia ACu AVia r 2 w d hpeff 1 kCu ACu (hpeff ) ACu wd z 1.86kox log10 1 w 0.66 w d 0.1 Chen, 2000 zBOT Typical values Th ,eff 25 32 K/mW (bot – top) Si © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 14 Many Shape Factors (Compact Models) © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 15 Thermal-Electrical Cheat Sheet © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 16 Obtaining the Temperature Distribution • Now we want temperature distribution T(x) in 1-D • Consider power in/out of a 1-D element • Simplest case: Si layer on SiO2/Si substrate (SOI) • Or interconnect on thermally insulating SiO2 © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 17 1-D Interconnect with Heat Generation L x x+dx d W Heat: Electrical: tox SiO2 Si dT dx dV I AJ A F A dx Q Ak Energy balance equation for 1-D element “dx”: pick units of J/cm3 or W/cm3 (W = J/s) T0 Energy In (here, Joule heat) = Energy Out (left, right, bottom) + Change in Internal Energy © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 18 Ex: 1D Rectangular Nanowire © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 19 1-Dimensional Heat Equation unsteady (transient) T k (k T ) Q ''' CV T t SiO2 T hp (k T ) Q ''' (T T0 ) 0 A g steady, with convection SiO2 © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 20 Interconnect Heat Loss and Crosstalk © 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 21 Carbon Nanotube (Cylinder) L T Pt g (a) SiO2 Si d A(kT ) p' g (T T0 ) 0 T ( x) T0 tOX p' I2 tSI Role of cylindrical heat spreading (shape factor!) (b) gox p' cosh( x / LH ) 1 g cosh( L / 2LH ) dR h 1 I2 2 dx 4q eff LH kA g kox 8t ln ox d 900 Role of thermal contact resistance Tmax T (K) 700 500 E. Pop et al. J. Appl. Phys. 101, 093710 (2007) © 2010 Eric Pop, UIUC ΔTC kA 300 -1 ECE 598EP: Hot Chips 0 X ( m) 1 2 dT dx C TC R C ,Th 22