Transcript asic

ASIC Replacement FPGAs
ASIC Features
ASIC Pricing
Immediate Production
HDL Design Flow
FPGA Flexibility at ASIC Prices!
Customer Presentation
Spartan FPGAs Replace
Gate Arrays in Production
Agenda
 Spartan Highlights
 Advantages vs. Gate Arrays
 Spartan Alternative to ASIC Conversions
 Spartan Replaces Obsolete Gate Arrays
How are Spartan FPGAs Different?
Spartan Matches Gate Array Die Size & Cost
 1995 - FPGAs cannot
compete with gate arrays



Older process than ASICs
Larger die
Not I/O pad limited
1995
FPGA
1.0u, 5K gates
160 I/O
 1998 - FPGAs compete


FPGAs are Fab process
drivers, replace DRAMs
Competitive die size with
similar number of I/O
1998
Gate Array
0.8u, 10K gates
160 I/O
SpartanXL,
Gate array,
0.35u, 10K gates 0.35u, 100K gates
160 I/O
160 I/O
Xilinx Spartan Series
5 Volt -> 0.5/0.35µ
3 Volt -> 0.35/0.25µ
System Gates
Logic Cells
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
2K-5K
238
Max Logic Gates 3,000
Flip-Flops
360
Max RAM bits
3,200
Max I/O
80
Performance
80MHz
3K-10K
466
5,000
616
6,272
112
80MHz
7K-20K
950
10,000
1120
12,800
160
80MHz
10K-30K 13K-40K
1368
1862
13,000
20,000
1536
2016
18,432
25,088
192
224
80MHz
80MHz
No Compromises:
Performance, RAM, Cores, and Low Price
Spartan Features:
On-chip SelectRAM™
 > 75% ASIC designs need RAM *
 SelectRAM advantages:



Dual Port Synchronous
Higher speed (to 100 MHz)
than RAM compilers
More flexible - numerous
distributed small RAMs
* Source: Dataquest
Spartan Extensive Core Support
 Spartan Core Advantages:
– Pre-verified in silicon
– Much lower cost than ASIC cores
– Simple distribution and licensing
Standard Bus Interface Products
Peripheral Component Interconnect
Bus (PCI)
Other Standard Bus Products
Digital Signal Processing
Correlators
Filters
Transforms
DSP Building Blocks
Communications & Networking Products
Asynchronous Transfer Mode
Forward Error Correction
Base-Level Products
Basic Elements
Math Functions
RISC CPU Cores
8-bit RISC core
Processor Peripherals
UARTs
Others
Spartan FPGAs
Designed for Low Price
 Smallest die of any FPGA with RAM
 Focused package offering
 Streamlined test process
 Optimized production flow
High-volume pricing < $3.00*
100K units
84PLCC, -3 speed
*
Spartan Price Reductions
Thru Technology
5V Price*
3V Price**
XCS05
$3.95
$3.50
XCS05XL
$2.95
XCS10
$5.50
$4.80
XCS10XL
$3.95
XCS20
$6.50
$6.50
XCS20XL
$5.45
XCS30
$7.95
$7.95
XCS30XL
$6.95
XCS40
$19.95 $13.80
XCS40XL
$9.90
* 100K units, end 1998
Cheapest pkg, slowest speed
** 100K units, mid 1999
Cheapest pkg, slowest speed
Cost Effective Cores
Replaces Standard Devices
XCS30XL
Price
Percentage of
Device Used
Effective
Function Cost
UART
$6.95
17%
$1.20
16-bit RISC Processor
$6.95
36%
$2.60
16-bit, 16-tap
Symmetrical FIR Filter
$6.95
27%
$1.90
Reed-Solomon
Encoder
$6.95
6%
$0.45
PCI Interface
(in PQ208)
$8.25
45%
$3.80
Core Function
Spartan Cost
Reduction Roadmap
Without Compromises
 ASIC prices
 Increased density & speed
 More SelectRAMTM
Spartan
 Added cores
$395*
Price
0.5 3LM
5 Volt
SpartanXL
$295*
0.35 5LM
Spartan-II
Spartan-III
$200*
3.3 Volt
$150*
0.25 5LM
0.2
2.5 Volt
1.8 Volt
1998
* Prices are per 5K system gates,
100K units, slowest speed, 84-PLCC
1999
2000
2002
Spartan Replaces
Low-Density Gate Arrays
Gates : I/O Fit
120
100
80
60
40
S40
S30
20
S20
10
0
S05
50
S10
100
150 I/O’s
200
250
300
Costs of ASIC Design
Like Buying a New Car
New Car Purchase -Expected Costs:
MSRP* $$$
Hidden costs:
Dealer rebates/ holdbacks..
And Unexpected costs:
Dealer prep, destination
charges, rustproofing ….
“Out-the-Door” Costs are Higher! = $$$
* Manufacturer’s Suggested Resale Price
Spartan Avoids
Expected Costs
Expected
Gate Array
Typical range of $15-20K
for low density gate arrays
Cores for ASICs can be up
Higher cost of
to 10x the cost.
cores & tools
Unix based synthesis tools
$50-100K
Insert scan and Scan and ATPG needed by
most ASIC production
ATPG
designs
NRE
Debug test
vectors
Debugging Test Bench is
major time element of ASIC
design
Spartan
No NRE
Cores for Spartan typical
range of $5-10K.
Complete design tool kit
<$10K
Spartan is 100% tested at
the factory
Test vectors not needed
for low density FPGAs.
Spartan Avoids
Unexpected Costs
Item
Gate Array
Multiple silicon 33-50% of designs need extra spin.
Extra spin costs 50% of NRE
spins
Spartan
Reprogrammable
Make mistakes with no cost
penalty
Perform 5 corner simulation (timing,
temp, voltage)
Planned for 1-2 weeks, takes 3-5
weeks
ASIC 1st time right methodology
Costs include:
Fab hot lot,
Risk mask/ wafers
Rush assembly
Cost range of $10-50K
Signoff not needed with
FPGAs
Large $
commitment
Big MOQ (20-30K pcs)
Big min shipment qty (10-20K pcs)
Non-cancellable – purchase all WIP
No MOQ needed for FPGAs
Demand
declines
Saddled with obsolete stock
No stock scrapping risks
with FPGAs
ASIC sign-off
Expedite proto
& initial
production
Prototype is immediately
available
Initial production quantities
ready when development
complete
Spartan Avoids
Hidden Costs
Item
Gate Array
ASIC Leadtimes
Production leadtimes ~8-16 wks Production leadtimes- 0-4
2-3 month delay
weeks to full production
= lost sales, profits
ASIC Inventory
Higher levels of stock than
FPGAs
High carrying costs
Ties up cash, reduced credit
May obsolete stock
Purchase customized wafers
(WIP)
Missed customer shipments
Takes engineers off new
projects
“Custom” product more difficult
JIT
Design change in
production
Supply Chain
Management
Spartan
Low stock, rely on JIT delivery
Stock at Disti locations
Cash & credit remain available
Easy change to prototype &
production.
No stock risk or missed
shipments
“Standard” product.
Off-the-shelf availability
Gate Array Cost Worksheet - New Designs
Gate Array Cost*
Typical Range
Customer Costs
FPGA
Expected costs:
NRE cost
ATPG from outside service/insert scan
Higher cost of ASIC cores
Generate & debug testbench
$15-20K
10-20K
50-150K
10-20K
______________
______________
______________
______________
None
None
50-70% less
None
15-20K
10-20K
______________
______________
None
None
10-40K
______________
None
50K+
10-20K
______________
______________
None
None
25K+
20K
20-30K
20K+
5-15K
______________
______________
______________
______________
______________
None
None
None
None
None
15-20K
10K+
______________
______________
None
None
$50K-150K
______________
None
Unexpected costs:
Silicon design iteration
(needed in 33-50% of ASIC designs)
Extensive customer sign-off (temp, V, MHz sim)
Expedite prototype/production
(hot lot, risk mask, rush assembly)
Large $ commitment
(MOQ, min ship qty, ties up cash)
Demand slackens (obsolete stock)
Hidden costs:
ASIC production leadtimes (8-10 wks;
lost sales, delayed market entry)
Design change needed in production
Scrap obsolete inventory
Conversion to ASIC costs/risks
Large ASIC inventory-carrying cost
Stock multiple ASIC codes:
(FPGA single bin stocking)
Difficult JIT delivery/supply chain management
Total Gate Array Costs - New Designs
* Assumption: Engineering cost @ $10K man/mo
Converging Methodologies
Design
Productivity
FPGAs close the design gap
Behavioral & IP
Behavioral & IP
ASIC
Methodology
Verilog , VHDL
Verilog , VHDL
Gates
Gates
Transistors
Gap
Schematic
Transistors
RTL
FPGA
Methodology
Boolean equations
1980
1985
1990
Year
1995
2000
Gate Array Design Flow
ASIC
Functional
simulation
VHDL/Verilog
Insert Scan
Synthesis
Create
test vectors
Simulation
ASIC vendor
Place & Route
Static timing
FPGA flow is similar, but:
•SCAN /test vectors not
needed for low densities
•Built-in JTAG
•Make mistakes, no penalty
•Concurrent engineering
•Real-time verification
Sign-off
ECO
Fab prototype
4 wk Lead-time
Initial production
8-10 wk Lead-time
Volume
Production
Customer quote:
“FPGAs – I love being able to
make mistakes. I can relax and I
don’t have to simulate as much. It’s
in my control.
ASICs – We sweat and
don’t sleep much until the ASIC is
available and tested.”
”
Spartan Supports
Gate Array Tools
 Synopsys, Cadence, Mentor, Viewlogic

93% of gate array designers use Synopsys
 Support of industry standards

EDIF, VITAL, VHDL, Verilog, SDF
Vendor
Simulation
Synthesis
Schematic
Other
Synopsys
VSS
FPGA Express
Vital Sim Models FPGA Compiler II
Design Compiler
Cadence
Verilog XL
Mentor
MTI ModelSim
V-System
Falcon Framework
Viewlogic
Viewsim
WorkView
Synergy
DesignWare
Motive static timing
Concept
Spartan FPGA Highlights

Spartan Replaces Gate Arrays
 Up to 40K system gates, 224 I/O

Spartan Meets ASIC Requirements





Performance to 80MHz
On-chip RAM
Silicon-verified Cores
Aggressive volume prices
Spartan FPGAs Avoid ASIC Costs
 Expected costs: NRE, scan, test vectors, ….
 Hidden costs: Leadtimes, inventory design changes, …
 Unexpected costs: Spins, sign-off, expediting, ..

HDL Design Flow with Broad 3rd Party Support
 Synopsys, Cadence, Mentor, MTI, Synplicity, Exemplar , ….
FPGA Cost-Reduction Paths
FPGA-to-ASIC Conversion
Costly
Path
FPGA
ASIC
Direct Translation or Retarget:
Engineering costs,
Conversion/ NRE fees,
4 month leadtime-to-production, design risks
New
Paradigm
Spartan FPGA into Production
No added engineering effort, no NREs,
Cost reductions through Spartan II, III, ….
Full production NOW!
Advantages of FPGAs
in Production
Spartan Avoids ASIC Migration Costs & Lead-times
 ASIC NRE/ Conversion fees

Typical range of $5-25K
 Customer engineering costs:




Verify new gate array design
Simulation, test program, sign-off
Characterize/ qualify new prototypes
Delay work on next project
 Lead-times for conversion-to-production
a best case of 4 months


Conversion time 3 weeks, proto 3 weeks,
production 10 weeks = 4 months
What is the product life? Is there a mid-life update?
Spartan Advantage
No Unexpected Re-design Risks
Result
Risk
Design relies on FPGA
features
 Features not found on ASIC
 Example: JTAG, on-chip RAM,
global reset, LogiCORE,...
Netlist is modified
 Often must be modified to
add functions
 Buffers and clocks are adjusted
to optimize drive capability
Timing issues
 Asynchronous timing
 Gated clocks
Porting CORES
 Timing changes between ASIC/
FPGA
 Complex licensing issues
 Xilinx / Alliance cores are not
transferable
Any mistake will exist in final ASIC
Gate Array Cost Worksheet - FPGA-to-ASIC Conversion
FPGA Conversion Costs*
Potential Impact
Actual
FPGA Costs
Expected costs:
NRE/conversion fees
Verify re-design (sim, vectors, & prototypes)
Insert JTAG
Higher cost of ASIC cores
$15-30K
Engineer’s time
Engineer’s time
50-150K
______________
______________
______________
______________
None
None
None
50-70% less
Higher volume
needed to
break even
______________
None
More costly changes/
No field updates
20K
10K
______________
______________
______________
None
None
None
Not work in-system
______________
None
Not work in-system
Not work in-system
Difficult licensing
______________
______________
______________
None
None
None
$50K-100K+
______________
None
Unexpected costs:
4 months conversion-to-production time
Conversion - 3 weeks
Prototype - 3 weeks
Production delivery - 10 weeks
Total time = 16 weeks
Hidden costs:
Lose reprogrammability advantage
Scrap obsolete inventory if design changes
Higher inventory costs/levels
Conversion re-design risks:
Converting FPGA features
(RAM, JTAG, reset)
Modify netlist - new buffers/
new drive capability
Device timing changes
Porting of FPGA Cores
Total ASIC Costs/Impact - Conversions
* Assumption: Engineering cost @ $10K man/mo
FPGA-to-ASIC Conversion
The New Paradigm: FPGAs in Production
 New paradigm - Spartan FPGAs in production


Spartan proto to production retains FPGA flexibility
Faster, less costly transition to volume production
 Cost reduction path with future Spartan Series


Spartan II in 1999
Spartan III TBA
 Spartan avoids redesign costs to gate array



Conversion fees
Added customer engineering
Long-lead-times for production
 Eliminates unexpected migration design risks


FPGA features difficult to emulate
Net list changes
Leading Suppliers Exit Gate
Arrays
 Deep sub-micron process increases mask and
wafer costs
 Accelerates pace to shut down older processes
 LSI & Motorola obsolete Gate Array families
No new Gate
Array since 1995
LL7000 Series (2.0 to 10K gates)
LL8000 Series (2.0)
LCA 10000 Compacted Array
(to 50K gates)
Exited Gate Array in 1996,
FPGA in 1998
HDC Series (1.0)
H4C Series (0.8)
H4CPlus Series (0.65)
H4EPlus Series (0.65)
M5C Series (0.5)
Example Flow
Converting Obsolete ASICs to an FPGA
RFQ
Package
Quote
Package
•Specifications
•Review RFQ Pkg.
•Design files
Business
•Timing Diagrams Technical
•Package Rqmts. •Prepare Quote:
•Quality Stds.
Price
•Operating Cond.
Delivery
•Interface Rqmts.
Design Reviews
•Quantity
Terms
•Schedule
Deliverables
Responsibilities
Design
•Create Design
•Simulate
•Debug
•Modify
•Test Vectors
•Documentation
Validation
Production
•Verify Design
•Verify Functionality
•System Test
•System Debug
•Verify Test Vectors
•Materials from:
Insight
Memec ICG
Memec
Customer
Responsibility Responsibility
Source: Memec Design Services
Obsolete ASIC to Spartan FPGA
“Made Easy”
 Leading suppliers exit gate arrays


Increasing gate array costs
LSI Logic and Motorola
 Spartan provides low-cost production solution




Add/delete features, integrate logic
Update design files to Verilog or VHDL for maintainability
Long term stable supply
No mask charges
 Xilinx Certified Design Centers have conversion experience



Design centers can provide turnkey service
Insight - Memec Design Services
Avnet - Design Services
Spartan FPGAs Displace
Gate Arrays In Production
 Spartan meets ASIC requirements

ASIC features, pre-verified COREs, aggressive prices, avoids costs
of ASIC design and enables flexible production
 Supports HDL tools and methodology

Broad 3rd party support, flexible design-flow
 Provides effective production cost-reduction
path

Avoids costs and risks of redesign to gate array
 Obsolete gate arrays convert to Spartan FPGAs


Majors exit gate arrays
Conversion to Spartan made easy by Xilinx Design Centers
Spartan Tool Alternatives
ASIC Tools
Spartan Tools
ASIC design tool:
FPGA Alternative:
Synopsys Design Compiler
Synopsys FPGA Express
& FPGA Compiler II
Synplicity, Exemplar
 Synopsys HDL synthesis
(93% of designs)
 VHDL/ Verilog = 50% shares
 New scripts needed
Synopsys Test Compiler
Test Compiler Not Needed
 Scan insertion
 Generate test vectors
 Increases die size/ impacts
performance
 Scan is not needed by FPGA
 100% factory tested
 Test vectors are optional
Spartan Tool Alternatives
ASIC Tools
Spartan Tools
ASIC design tool:
RAM compiler
FPGA Alternative:
Xilinx compiler
 Expands used gates
 Lower performance RAM
 On-chip SelectRAM
 No performance impact
HDL simulators
HDL simulators
 Cadence VerilogXL
 MTI, more….
 Cadence VerilogXL
 MTI, more …..
Static timing
Static timing


 Quad Tier 1 in Alliance 2.1
 Xilinx Static Timing
Quad Motive
Synopsys Primetime
Cores
Cores




In-house
3rd Party
LogiCORE
AllianceCORE
There Are Design
Methodology Differences
HDLs were developed for ASICs


Achieving 66MHz speed with ASIC is easy
FPGAs require more structured techniques
FPGA design optimization
requires architectural “know-how”
–
–
Complex functions operate > 50MHz
Critical design technique is pipelining
FPGA offer freedom to do design,
not under gun till working parts
Extensive Core Support for Spartan
Partial list of Spartan Cores
Peripheral Component Interconnect Bus (PCI)
PCI32 Spartan Master & Slave Interfaces
Other Standard Bus Products
IIC
Digital Signal Processing
Correlators
One Dimensional RAM Based Correlator
One Dimensional ROM Based Correlator
Filters
Comb Filter
16-Tap, 8-Bit FIR Filter
Serial Distributed Arithmetic FIR Filter
Dual Channel Serial Distributor Arithmetic FIR Filter
Parallel Distributed Arithmetic FIR Filter
Transforms
DFT Core, (Real Data In, Complex Data Out)
FFT Core, (1024 Points)
DSP Building Blocks
SDA FIR Control Logic
Sine/Cosine
Processor Products
RISC CPU Cores
Communications & Networking Products
Asynchronous Transfer Mode
CRC10 Generator and Verifier (CC-130)
CRC32 Generator and Verifier (CC-131)
Forward Error Correction
Reed-Solomon Decoder
Reed-Solomon Encoder
Viterbi Decoder
Base-Level Products
Basic Elements
Constant
Two Input Multiplexer
Three Input Multiplexer
Math Functions
1's and 2's Complement
Accumulator
Scaled by 1/2 Accumulator
Registered Adder
Registered Loadable Adder
Registered Scaled Adder
UARTs
XF-8250 Asynchronous Communications Element
M16450 Universal Asynchronous
Receiver/Transmitter
Processor Peripherals
C2910a Microprogram Controller
M8254 Programmable Timer
M8255 Programmable Peripheral Interface
Spartan FPGA Comparison
vs. Gate Arrays
Design:





Test vectors/ ATPG
Prototyping time
Silicon design change
Cost of iterations
Cost of CORES
Spartan
Gate Array
None
Hours
Hours
None
Low
Long
Weeks
Weeks
High
High
Excellent
Excellent
Excellent
Excellent
Low
Poor
Poor
Poor
Poor
High
None
Low
High
High
Production:





Fast production ramp
Lead-times
JIT delivery
React to mkt changes
Min order quantities
Inventory:


Cost of scrap inventory
Carrying costs
Spartan Advantages Summary
In Design:





Eliminates NRE
Immediate prototypes
No test vectors/ ATPG needed (100% factory tested)
No penalty for design spins with reprogrammability
Broad and verified portfolio of COREs
In Production:
 Fast time-to-volume production with “off the shelf”
availability
 Immediate market penetration
 Facilitates JIT delivery
 No scrapping inventory
 Enables field product updates
FPGA Flexibility at ASIC prices
ASIC Replacement FPGAs
ASIC Features
ASIC Pricing
Immediate Production
HDL Design Flow
FPGA Flexibility at ASIC Prices!