Transcript ppt

Advanced Digital Design
The Need for a Design Style
by A. Steininger
Vienna University of Technology
Outline

Skew versus consistency

The need for a design style

Hazards, Glitches & Runts
Lecture "Advanced Digital Design"
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Design: Boolean Logic

unambiguous functional description

combinational logic: truth table

sequential logic: state diagram

technology agnostic

temporal relations
are not relevant
(just sequence)
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Implementation: Physics
 There is a signal delay


in all transistors

through all interconnect
This signal delay

cannot be eliminated

is indeterministic
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Fundam. Speed Limitations

EM wave propagation
Information can never travel faster than
with speed of light. (20cm/ns)

Charging effects
Charging of a capacitance with limited
current takes time. (Dt  t = RC)

Charge movement
Movement/diffusion of charges in semiconductor has limited speed. (0,1mm/s)
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Can we predict Delay?

Gate Delay



Interconnect Delay




logic depth (<=optimization & mapping)
data dependent delay (dynamic!)
geometry (lengths, capacitances)
vias, switches
crosstalk (dynamic!)
PVT Variations



Process variations
supply Voltage
Temperature
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Skew Prediction ?

Signal delay is difficult to predict, it even
varies with operating conditions & data.

The delays along two individual signal
paths will never be the exactly the same.

The (maximum) difference among two or
more signal paths of interest – termed
„skew“ – is even more difficult to predict.
?
?
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Skew and Consistency

Data consistency

When individual data items are
interpreted together, these must
belong to the same context
they must be temporally correlated

x- and y-coordinates of a moving object

bits of a data word
Skew distorts temporal correlation
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Consistency – an Example
sending
00 10 11 10 00
Delay
receiving
00 10 11 10 00
Skew
receiving
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00 10 01
11 00
10 00
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Consistency & Glitches
0
1
A
1
0
&
1
10
Y = A  A  0
0

DT
Everything OK for the steady state
A dynamic analysis reveals glitches!
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Pulse & Glitch

Pulse:
transition followed by
opposite one



PW
„positive“: 
„negative: 
Pulse width PW:
time distance between
these transitions

Glitch:
spurious pulse,
usually undesired
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Danger of a Glitch

Glitch becomes dangerous when
converted from
spurious to steady state

by using the transition (control signal)
or

by capturing its value (data signal)
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Types of Delay

Pure delay (transport delay)



simple „time shift“ of all transitions
pulses of any width are transported
Inertial delay (component delay)


transition only made if still required after delay
pulses shorter than the delay are suppressed
D
D
pure
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D
D
pure = inertial
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D
inertial
13
Delay types in Reality

Pure delay




much related to speed-of-light delay
typical for wires with small RC
increasing relevance for newer technology
Inertial Delay



much related to RC delay
typical for gates (& wires with high RC)
considered more relevant in practice
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Runt Pulses

when decreasing width PW of pulse applied
to real circuit,

large PW => pulse definitely recognized

small PW => pulse definitely ignored
(circuit‘s inertial delay)


for some PW in between
output will be very short and
not reach full amplitude
 RUNT pulse
VDD
VSS
a runt will be marginally recognized (may or
may not) by subsequent inputs
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Design: Boolean Logic

unambiguous functional description

combinational logic: truth table

sequential logic: state diagram

technology agnostic

temporal relations
are not relevant
(just sequence)
cannot be expressed!
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The Consequences
A

Boolean Logic describes
I/O-mapping without
consideration of time
A
0
0
B
0
0
C
0
1
F
0
0

This implies continuously
consistent inputs

Skew inevitably causes
inconsistency at the
inputs and hence
invalid dynamic outputs
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
1
0
1
0
1
 glitches & runts
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Why not avoid Skew?

Just change a single bit
at a time, then skew
does not take effect
Skew
Data permanently
consistent
( „Huffman Circuits“)
A
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Still glitches…
1 X
1 Y
1 Z
 W
&
K
&
L
0
>=1

single
transition
&
M
A
Glitch!

Forks turn single transitions into multiple ones !
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Some First Conclusions…

Boolean Logic is a powerful method for
functional description, but

it does not take care of timing issues

Timing issues are relevant,
their ignorance leads to
glitches, runts and inconsistent data

We need a some form of „discipline“ when
designing a real circuit

It makes sense to investigate further into
glitches
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Combinational Hazard

Potential for glitches to occur in a circuit,
depending on relative path delays

Glitch is a manifestation of a hazard in a
physical implementation of the circuit

Actual manifestation may depend on

input patterns

actual delay values (PVT variations)
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Types of Comb. Hazards

static 1:
input change retains
output at 1, but
negative glitch occurs

static 0:
same for output 0 and
positive glitch

dynamic:
glitch occurs prior to
desired output change
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Static 0 Hazard

Fundamental circuit structure:
A



1
&
Y = A  A  0
fork
inversion on one lane
reconvergent into AND gate
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Static 1 Hazard

Fundamental circuit structure:
A



1
>=1
Y = A  A  1
fork
inversion on one lane
reconvergent into OR gate
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Eliminating SC Hazards
D1
1
A
&
Y
D2



How to choose delay constraints ?
no solution for constant delays
solvable for edge-dependent delay:
 : D1 > D2  : D1 < D 2
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Delay constraints

Absolute timing contraints:
keep skew between different
paths within a certain limit
 generally not achievable

Relative timing constraints:
keep one path slower than the other
 generally possible,
particularly in combination with input restrictions
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Detection in Schematics
A
1
>=1
B
&
&
C
>=1
D
1
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Y
&
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Detection in Equation
Y = [(C  D)(B  D)]  (A  B  C)

assign input values until B and B
remains:
A = 0; C = 0; D = 1
(enabling condition, need not exist)
Y = B  B
static 0 hazard
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Detection in KV-Diagram
A
C
B
1
1
1
D
1
static 1 hazards
1
1
1
1110  1111
0110  0111
remedy:
redundant term
static 0 hazards
use KV for Y
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Another Example
W
WX
00
YZ
00
01
11
Y 10
1
1
WX
01
11 10
1
1
1
1
1
1
YZ
00
1
1
01
Z
11
Y 10
X
A
1
1
01 11 10
1
1
1
1
1 1
1 1
Z
X
F = (X  Y  Z) 
(W  Z)  (W  Y)
Lecture "Advanced Digital Design"
00
W
F = (X  Y  Z) 
(W  Z)  (W  Y)
 (Y  Z)  (W  X  Y)
 (W  X  Z)
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Systematic Approach

define a notation to describe all
scenarios of interest


study propagation


9-valued logic
extended truth table
identify critical input scenarios

satisfyability problem
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9-valued logic
1
0


stable high
stable low
rising edge
falling edge
S1
S0
static-1-hazard
static-0-hazard
D+ dynamic hazard, rising edge
D- dynamic hazard, falling edge
*
any value at all
ordering: S0 > 0, S1 > 1, D- >
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, D+ >
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Truth Table „AND“
&
0
1


S1
S0 D+ D-
*
0
1


S1
S0
D+
D*
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Truth Table „AND“
&
0
1


S1
0
0
0
0
0
0
1
0
1



0
S0
0




S0

S1
0
S1
S0 D+ D-
*
S0
D+
0
0
S0 S0 S0 S0 S0 S0 S0
D+ S0 D+ D+ S0 D+ S0
*
*
D*
0
0
D*
*
*
Lecture "Advanced Digital Design"
S0
*
0
S1
S0 D+ D-
*
D-
S0 S0
D-
*
D+ S0 D+ S0
*
D*
© A. Steininger / TU Vienna
0
0
*
0
D- D+ S1
D*
S0 D+ D-
S0 S0
*
*
D*
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Propagation Analysis 1
A


1
&
S0
Y

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Single Input Change (SIC)

So far:
glitch due to single input signal changing

Watch out for reconvergent paths:



Fork: put single transition on concurring paths
Join: recombine the two transitions, whose
temporal relation has been distracted by skew
If we allow more input signals to change


we do not need the fork
by moving the relative position of the inputs we
gain even more freedom in arranging adverse
timing conditions
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Multiple-input change
A
1
>=1
B
&
&
C
>=1
D
1
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Y
&
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MIC Detection in Equ.
Y = [(C  D)(B  D)]  (A  B  C)

assign input values for A and B:
A = 1; B = 0
Y = C  D
static 0 hazard:
1000  1011
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MIC Detect in KV-Diag.
A
C
B
1
D
1
1
1
1
1
1
There is a
shortest path
leading over
other logic
value
„functional
hazard“
cannot be
eliminated
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Handling Static Hazards

Elimination


Defeating




add terms (in sum-of-products implem.)
not always possible for MIC
disallow enabling conditions
disallow critical transition(s)
restriction of operation
add timing constraints
needs to be asymmetric
Filtering (i.e. adding inertial delay)
limited effect only, slows down circuit
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Dynamic Comb. Hazard

Fundamental circuit structure:
glitch producer (010)
1
A
&
>=1
edge
producer
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Dynamic Comb. Hazard

Fundamental circuit structure (dual):
glitch producer (101)
1
A
>=1
&
edge
producer
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Dynamic combin hazards
1
A
D1
D2
D3
&
>=1
 safe if D1 < D2 or D3 < D1
(no glitch)
(edge masks glitch)
 safe if D1 > D2 or D3 > D1
all safe if D1 > D2, D3 or D1 < D2, D3
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Extension to MIC
1
A
A
1
&
&
B
>=1
>=1
C
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Dynamic Hazards ?
A
1
>=1
B
&
&
C
>=1
D
1
Lecture "Advanced Digital Design"
Y
&
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Handling Dynamic Hazards

Elimination


not always possible for MIC
Defeating

relative constraints sufficient!
in complex circuits unclear if constraining
always possible: constraints may be
contradicting BUT not all input patterns occur



disallow enabling patterns
disallow critical transitions
Filtering
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What about „real“ HW?
Example AOI gate:
A
B
A
&
>=1
z
B
C
C
z
Switching involves 2 transistors
per input
 even more delay path combinations
(p-stack, n-stack)
C
A
B
 may lead to tristate, short, glitch,…
 proper cell layout is crucial!
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So why a Design Stlye?

Skew is inevitable and unpredictable

It causes inconsistent transient states

Their logic evaluation causes runts & glitches

These are harmful if converted to stable states

There are methods to detect and prevent
glitches; those are far from perfect

Specific precautions are needed, as Boolean
Logic does not help here
 we need some discipline, a design style
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Without a Design Style…

…combinational gates may, due to race
conditions, receive contradictory signals
„simultaneously“ on different inputs, hence

create glitch or runt pulses that may

be converted into erroneous stable states or

even cause metastability in storage loops.

These glitches, runts and/or manifestations
of metastability may propagate, and

they may be subject to „Byzantine“ interpretation, causing further erroneous states.
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