Transcript Slides

Strips and Pixels Detectors
Associated Electronics
Jean-François Genat
LPNHE Paris
Louvain la Neuve,
Jan 16th 2008
J-F Genat, LLN Jan 2008
Outline
Solid-state vs Gaseous, basics
Strips
Timing
Pixels
Monolithic
DEPFETs
SOI
Hybrids
3D detectors
Readout electronics
Perspectives
J-F Genat, LLN,
Jan 16th 2008
Solid state detectors vs Gaseous
Gaseous
Silicon
Ionization energy
20 eV
3.6 eV
Primary ionization
3e-/mm
60k e-/mm
Amplification
100k
No
Carriers velocity
50 mm/ns
500 mm/ns (electrons)
Signal processing
integration
No
Yes
Radiation hardness
Yes
No, if not designed for
J-F Genat, LLN,
Jan 16th 2008
Exceptions: DEPFETs
(APDs, Silicon PMTs)
Basic mechanisms
Primary ionization
Low electron-hole pair generation energy: 3.6 eV (Silicon)
High loss/length: 1 MIP = 60k e-/mm
Small range d rays, high position resolution using thin detectors
Collection
- Drift under depletion field: reverse biased PN junction
Voltage needed depends upon resistivity : high resistivity Silicon
(1e4 W/cm) to deplete at low voltages (100V)
Drift velocity saturates: v = m E, 1/r = Nq m
-
Diffusion
Total collected charge = primary ionization
Unless reduced by :
- recombination with impurities
- radiation damage
Current signal as large as:
- number of moving carriers,
- electric field (as high as closer to small electrodes)
J-F Genat, LLN,
Jan 16th 2008
Noises
Sources of noise
Parallel
Series
Input noise
Detector leakage current
Biasing resistor
Electrode resistance
input transistor (thermal, 1/f)
« System » noise
All other noises !
Parallel 1/f
Series
Charge amplifier f
Reduce detector capacitance (segmentation helps)
Use high good quality material (leakage current)
Use appropriate shaping times
H. Spieler
http://www-physics.lbl.gov/~spieler/Heidelberg_Notes/pdf
J-F Genat, LLN,
Jan 16th 2008
Outline
Solid-state vs Gaseous, basics
Strips
Timing
Pixels
Monolithic
DEPFETs
SOI
Hybrids
Semi-3D, 3D detectors
Readout electronics
Perspective
J-F Genat, LLN,
Jan 16th 2008
Silicon strips DC coupled
Single sided
Double sided
DC or AC coupled
G. Lutz Semiconductor Radiation Detectors.
Springer Verlag 2001
Single sided
DC coupled
Amplifier
bias voltage
al
n
Fully depleted
PN junction
P+
al
n+
+V
DC leakage current flowing through amplifier may saturate
particularly under irradiation
J-F Genat, LLN, Jan 16th 2008
AC coupled strips
AC coupled
No DC flowing through insulated amplifiers
Need for biasing resistors
0V
a
l
SiO2
n
P+
al
20% more expensive
’’pinholes’’ through oxide
J-F Genat, LLN,
Jan 16th 2008
n+
+V
Silicon strips parameters
Size
DC or AC coupled
Pitch
Substrate resistivity
Capacitance to substrate
Interstrip capacitance
Full depletion voltage
Thickness
Leakage current
Junction breakdown
Interstrip resistance
Edgeless
Defective strips
J-F Genat, LLN,
Jan 16th 2008
100 x 100 mm2 (6-8’’ wafers)
20-200mm
2-10kW/cm
100fF/cm
1pf/cm
60-100V
50-300 mm
50nA/cm2 at 100V bias
>200V
> 2 GW
< 10 mm
<1%
Silicon strips space resolution
Digital readout (ATLAS, CERN ABCD chips):
s =d / 12
d= 50 mm, s = 15 mm
Analog readout (CMS, RAL APV25 chips):
Several adjacent strips collect the signal:
Centroids
Improved space resolution:
s = <10 mm
ATLAS Unno et al. NIM A453 pp109-120
CMS
K. Klein. IECHEP 2005, Lisboa
J-F Genat, LLN,
Jan 16th 2008
Magnetic field effect
Degrades space resolution
(S. Cucciarelli)
J-F Genat, LLN,
Jan 16th 2008
Silicon strips modules
CMS
Radiation hardness
is a big issue, as close to the beam
J-F Genat, LLN,
Jan 16th 2008
(K. Klein)
Outline
Solid-state vs Gaseous, basics
Strips
Timing
Pixels
Monolithic
DEPFETs
SOI
Hybrids
3D detectors
Readout electronics
Perspective
J-F Genat, LLN,
Jan 16th 2008
Timing
The faster detector and front-end electronics,
The better the timing
Obvious, but still to keep in mind…
J-F Genat, LLN,
Jan 16th 2008
Rise time and noise
noise
1
Slope 1/t
dA
d t = d A .t
dt
t
sA
Threshold
st
s A  s t = s A .t
Effects of noise
Time spread proportional to rise-time and noise
J-F Genat, LLN,
Jan 16th 2008
Amplitude, rise-time
Amplitude and/or Rise-time spectra translate into time spread
J-F Genat, LLN,
Jan 16th 2008
Fast detectors
Moving charges:
d
i=nqv/d
Rise-time
transimpedance
Bias
di/dt= q [ n dv/dt + dn/dt v]
collection multiplication
Maximize
n
dv/dt
primary ionization, detector thickness
qE/m electric field
- Electron multiplication
- High electric fields, segmented electrodes
- Reduce collection distance d
- Detector capacitance (signal/noise)
- Landau amplitude distribution (rise time spreads)
J-F Genat, LLN,
Jan 16th 2008
Gaseous vs Silicon
Signals (e-) Rise-time Time resolution
Gaseous
•
•
MWPCs
RPCs
106
107
3ns
1ns
500ps
100ps
Silicon
• Strips
• 3D Silicon
• Silicon PMs
104
104
107
5 ns
1ns
1 ns
2 ns
?
100 ps
J-F Genat, LLN,
Jan 16th 2008
Time picking techniques
Time picking:
Leading edge
Zero crossing
Constant fraction
Multiple thresholds
Sampling
Leading edge vs CFD
J-F Genat, LLN,
Jan 16th 2008
Sampling vs CFD
MATLAB Simulation with Silicon signals
Better compared to CFD by a factor of two depending
on noise properties and signal waveform statistics
- MATLAB simulation package
J-F Genat, LLN,
Jan 16th 2008
Expected time resolution with Silicon
Simulated time resolution using sampling
- S/N =25
- 16 samples
- 40 ns shaping
1 ns time
resolution
J-F Genat, LLN,
Jan 16th 2008
Timing using Silicon strips
Using sampling at 25ns rate, digitization and signal processing,
a time resolution of 2ns id obtained (CMS detectors + APV25 chip)
using a deconvolution algorithm
M. Friedl et al NIM 572 pp 385-387
J-F Genat, LLN,
Jan 16th 2008
Coordinate along the strip
SPICE
L =50nH
R =5 W
Ci=500 fF
15 ns
120cm
V = c/3.7
Cs= 100 fF
V = 1 / LC
V = c/4.7
8 cm /ns
J-F Genat, LLN,
Jan 16th 2008
Measured Pulse Velocity
V = 4.5cm/ns
Threshold
4.5 ns/cm
moving
a laser
diode along
cm
MovingMeasured
a laser diode
along
the Silicon
strip24
detector
J-F Genat, LLN,
Jan 16th 2008
Outline
Solid-state vs Gaseous, basics
Strips
Timing
Pixels
Monolithic
DEPFETs
SOI
Hybrids
3D detectors
Readout electronics
Perspective
J-F Genat, LLN,
Jan 16th 2008
Monolithic Active Pixels Sensors (MAPS)
Integrate pixel detector and readout electronics
using a single standard opto CMOS process (cheap)
Matrices of 25 x 25 microns pixels
n+
n well
Built-in 2D device
Detector segmentation highly improves Signal/noise
p epi
P sub
Opto-CMOS allows pixel signal processing
Slow collection (diffusion)
Slow readout (unless on-pixel sparsifier implemented)
Power needed by amplifiers (can be cycled)
Dulinski et al. Trans Nucl Sci V49 N2 p601
J-F Genat, LLN,
Jan 16th 2008
DEPFETS
One MOSFET on top of a fully depleted PN junction:
MOSFET current is modulated by the deposited charges stored in the bulk
under the channel: amplification . Multiple readout possible (reduced noise)
using two ping-pong DEPFETs.
Thickness down to 50 mm
4000 e-/MIP
Noise down to ¼ electrons ! Wolfel et al. NIMA253, 356-377
Source
p+
1m
Gate
Drain
Clear
n+
p+
n+
p
Internal gate
p
n+
n+
---
Gain: 500pA/e-
Bulk
MIP
n-
+++
p+
G. Lutz Semiconductor Radiation Detectors.
J-F Genat, LLN,
Jan 16th 2008
Springer Verlag 2001
50m
DEPFETS Readout
Readout chip
•
•
•
•
•
•
•
•
Current based
3-fold sampling
Noise 45 nA (<100 e- equivalent)
Signal/noise = 40
Mixed signal FIFO
Analog pedestal subtraction
Zero-suppression up to 110 MHz
4.5 x 4.5 mm2
250nm CMOS
M. Trimpl et al. NIMA 511 p257
J-F Genat, LLN,
Jan 16th 2008
Silicon on Insulator (SOI)
Superimpose:
-
CMOS process on low resistivity Silicon
Oxide (100-200nm)
High resistivity Silicon (detector)
Allow connections through oxide
PMOS
gnd
n well
p
NMOS
gnd
oxide
p+
p+
n detector
al
+HV
J-F Genat, LLN,
Jan 16th 2008
SOI features
Full thickness of fast collection detector
High performance CMOS electronics available
Availability of SOI wafers from industry (SOITEC)
Processes available: Japan OKI 150nm, US ASI 180nm.
100% fill factor
Not so radiation hard (oxide)
Not so cheap
J-F Genat, LLN,
Jan 16th 2008
SOI pixels
Fermilab pixel design:
64 x 64 matrix of
26 x 26 mm counting pixels (12bit, max 1MHz)
350 mm detector thickness
Pixel includes:
Amplifier 150 mV/1k eCR-RC shaper150ns peaking time
Discriminator
12bit counter
Y.Arai et al. NSS 2007 N20-2 pp 1040
ASI US
OKI Japan
J-F Genat, LLN,
(Numbers from Ray Yarema, FNAL)
Jan 16th 2008
Hybrid pixels
Flexibility for detector/electronics process choice
Readout chips available (CERN), but fixed pixel size
Radiation hard (as far as detector and electronics are,
but the choice is more open)
Pixel level bump bonding connexions
Mature technology
J-F Genat, LLN,
Jan 16th 2008
Hybrid pixels at LHC
Detector and electronics as two independent Silicon structures
ATLAS Vertex detector:
- Detector:
ATLAS rad-tol: Partially depleted n+ on_inverted_n on
Fz-oxygenated Silicon after irradiation
- Electronics:
FE-I3 chip IBM 250nm (LBL Bonn CPPM)
CMS
Bump-bonding (Bonn – IZM)
Detector:
Electronics:
Cz-oxygenated
IBM 250nm (PSI)
L. Cremaldi et al. NIM 511-1, pp64-67
J-F Genat, LLN,
Jan 16th 2008
FE-I3 chip (LBNL, Marseille, Bonn)
• 18 x 160 pixels columns, active area 8 x 7.2mm2
• Time over threshold (7 bits)
• Level 1 buffering: 3.2ms. Max rate: 0.15 hit/BC/column pair=1.35
hit/BCO/chip.
• Trigger output as a single fast OR bit of all (selectable) pixels.
400 mm
7.2mm
50 mm
7.4 mm
10 mm
100 mm
8 mm
1100 mm
Output data format:
| Header 1 | BC Id 4 | row 8 |column 5 | Parity 1 | ToT 7 |
J-F Genat, LLN,
Jan 16th 2008
I/O pads
ATLAS pixel module
•
Pixel module (50,000 pixels)
J-F Genat, LLN,
Jan 16th 2008
Outline
Silicon detectors
Solid-state vs Gaseous, basics
Strips
Timing
Pixels
Monolithic
DEPFETs
SOI
Hybrids
3D detectors
Readout electronics
Perspective
J-F Genat, LLN,
Jan 16th 2008
3D Silicon
J-F Genat, LLN,
Jan 16th 2008
3D Silicon detectors
Full 3D: Charges move parallel to the detector plane instead
transverse, the field created using vertical electrodes
through the detector (MEMS technology). Built-in pixels.
Semi-3D:
The backplane is still an electrode.
Electrons are collected by vertical electrodes, holes by backplane.
J-F Genat, LLN,
Jan 16th 2008
3D Active edges Silicon
Full 3D:
Both type of carriers collected by electrodes of two types
Active edges allow sensitivity to 5 microns from the cut,
Abutt detectors without dead zones.
J-F Genat, LLN,
Jan 16th 2008
3D Silicon
Collection distance reduced by 10:
-
Faster (1-2ns rise-time)
Position resolution down to 10-15 mm in the two dimensions.
Same collected charge (24k electrons/300 mm)
More radiation tolerant detectors (1015 n/cm2).
Depletion voltage reduced to a few Volts.
Any connexions between electrodes are possible (as long as the
total capacitance remains small, if not noise increases)
- Active edges (conducting): edgeless capability down to 10 mm.
- Readout using CMOS chips available at CERN (ATLAS pixels)
- Moderate passive cooling.
J-F Genat, LLN,
Jan 16th 2008
Available 3D detectors
7.4 x 8mm2 detectors bump-bonded to FE13 chips (CERN)
400 x 50 mm2 pixels
Plans to reduce pixel size to 50 x 50 mm2
400 mm
Active area
50 mm
7.2mm
7.4 mm
10 mm
100 mm
8 mm
1100 mm
J-F Genat, LLN,
Jan 16th 2008
I/O pads
220m Roman Pots at ATLAS
8m
IP
220m
One horizontal pot and two vertical pots at 216 and 224 m on each arm
with detectors as close as possible to the beam: 10 s = 1mm
Two Vertical pots
One Horizontal pot
3cm
Silicon detectors
J-F Genat, LLN,
Jan 16th 2008
3D Silicon detectors for RP 220
J-F Genat, LLN,
Jan 16th 2008
Roman Pot Layout
Read out and Trigger LOGIC (FPGA)
Power and Clock distribution
Slow control
Cooling
MCP-PMT
Read Out
ASIC
64 Ch.
8x8
Pixels
Radiator
Light
Guide
X
Edgeless
Silicon
X
To
Alco
ve
FE ASIC
(PA,SH,Pipeline)
Plus FAST OR
2,54 x 2,54 cm
Beam
4,5 cm
P. Le Dû
J-F Genat, LLN,
Jan 16th 2008
Acceptance for diffracted protons
Acceptance for diffracted p[rotons at 220m
Simulation
J-F Genat, LLN,
Jan 16th 2008
3D Silicon layout
J-F Genat, LLN,
Jan 16th 2008
Silicon Manufacturers
Hamamatsu
Japan
Canberra
Belgium
SINTEF
Norway
Micron
UK
CSEM
Switzerland
VTT
Finland
CiS
Germany
IST
Italy
STM
France
J-F Genat, LLN,
Jan 16th 2008
3D
3D
Outline
Solid-state vs Gaseous, basics
Strips
Timing
Pixels
Monolithic
DEPFETs
SOI
Hybrids
3D detectors
Readout electronics
Perspective
J-F Genat, LLN,
Jan 16th 2008
Digital sampler chip for Silicon strips
Technology CMOS 130nm
J-F Genat, LLN,
Jan 16th 2008
Digital sampler architecture
Channel n+1
‘trigger’
Sparsifier
S aiVi > th
Time tag
Channel n-1
reset
Wilkinson
ADC
Calibration
Control
reset
Analog samplers, slow, fast
Ch #
Waveforms
Strip
Preamp +
Shapers
Counter
Charge 1-40 MIP, S/N~ 15-20, Time resolution: BC tagging,
Technologies: Deep Sub-Micron CMOS 180-130nm
Deep Sub-Micron CMOS
LPNHE Paris
J-F Genat, LLN,
Storage
Jan 16th 2008
fine: ~ 2ns
Digital sampler prototype chip layout
Technology CMOS 130nm
J-F Genat, LLN,
Jan 16th 2008
Prototype Sampler chip beam tests
120 GeV pions beam tests
S/N= 18
Detectors+ 130nm chip
J-F Genat, LLN,
Jan 16th 2008
Issues
Inter-layers vias through oxide (etching)
Wafer thinning to facilitate through wafer vias
Alignment (< 1mm)
Present:
6’’ wafer thinned to 6 mm, mounted on 75 mm Kapton !
J-F Genat, LLN,
Jan 16th 2008
Outline
Solid-state vs Gaseous, basics
Strips
Timing
Pixels
Monolithic
DEPFETs
SOI
Hybrids
3D detectors
Readout electronics
Perspectives
J-F Genat, LLN,
Jan 16th 2008
MAPS
Faster collection time by drift in a depleted PN junction
Integrate pixel discriminators:
Sparse readout to fasten the readout
Improve fill factor
Integrate pixel DAC for threshold match
Storage
350nm standard HighVoltage CMOS process
(used for I/Os)
Mannheim Germany
I.
J-F Genat, LLN,
Peric IEEE NSS 2007 N20-1 pp1033-1039
Jan 16th 2008
3D Silicon
Merge pixels and strips
Pixels top
Strips underneath
Readout with bump-bonded pixel chip, wire bonded
to strip readout chip
Improved space resolution, trigger capabilities with the
strips.
C. Da Via’ 2005
J-F Genat, LLN,
Jan 16th 2008
Silicon at low T
Electron and hole mobilities in Silicon vs dopants densities
at various temperatures
J-F Genat, LLN,
Jan 16th 2008
Front-ends
NA60 AFP chip (CERN)
Cryogenic Silicon beam tracker for high intensity proton
beam and heavy ions hodoscopes
•
•
•
•
•
•
•
32 channels 0.25mm CMOS
T=80-300K
Transimpedance amplifier optimized for 4pF input
CMOS 250nm
Gain:
10mV/MIP
Noise:
350 e- (@ 300K)
Fall time:
3ns @ 300K, 1.5ns @ 130K
Radiation hard to 1015 p/cm2
Designed for 20 mm pitch Silicon strips detectors
Rencently tested with 3D detectors
G. Anelli et al
A high speed low-noise transimpedance… NIMA 512 1-2 pp117-120
J-F Genat, LLN,
Jan 16th 2008
Silicon readout
Merge low-noise amplification and sampling
Increase number of channels up to 1k
Implement low level Digital Signal Processing
Calibrations, centroids, fits
Flip-chip 3D interconnect
Equip on-detector Silicon strips readout
3D interconnect to pixels (3D or others)
J-F Genat, LLN,
Jan 16th 2008
Signal processing
• Fast samplers in CMOS technology
• Saclay (France)
• Germany
• Hawaii
2 GHz 12 bits
5 GHz 12 bits
6 GHz 10 bits
Push sampling speed up to higher frequencies:
Get Charge and Time with ultimate precision
J-F Genat, LLN,
Jan 16th 2008
Vertical integration
As device feature size cost increases, vertical integration
allows stacking any processes:
DEPFET + CMOS/SOI
CCD + CMOS/SOI
MAPS + CMOS/SOI
Ray Yarema, FNAL
Lincoln Labs
IZM Germany
Digital
Analogue
Sensor
Solves the 2D interconnection bottleneck:
- Reduces I/O pads, crosstalk, power, increases speed for
same functionnality
J-F Genat, LLN,
Jan 16th 2008
Vertical integration references
Ray Yarema
Marcel Demarteau
Fermilab
’’
R. Yarema, 3D Integrated Circuits for HEP,
6th Front-End Electronics Workshop Perugia 2006
C.Bower et al, High Density Vertical Interconnects
56th Electronics Components TC Conference May 30th-June 2 2006 San Diego
A.
Klump, ‘’3D System integration’’, FEE Perugia 2006
B. Aull et al. Laser Radar Image based on 3D APDs IEEE SSCC 2006, p26
J-F Genat, LLN,
Jan 16th 2008
The end…
Lots of ideas
Technology exploding
So
much to do…
Thanks !