Transcript HSIM - EDACafe.Com

Next Generation Full-chip
Circuit Simulation and Analysis
December 2002
© Copyright Nassda Corporation
Who is Nassda?
We are a fast-growing provider of
full-chip circuit verification and
analysis software for complex
nanometer ICs.
© Copyright 2002 Nassda Corporation
2
Strong Business Performance
• Over 150 customers
 18
of top 20 semiconductor companies rely
on Nassda
• Enabling tapeout success for our
customers
• 2nd fastest growing EDA company in
2001†
• No. 4 IPO across all industries in 2001
†Dataquest
© Copyright 2002 Nassda Corporation
3
Customer Satisfaction
• Top technical team from industry and
academia committed to customer
success
• No. 1 in Repurchase loyalty

Would buy from vendor again
• No. 2 in Referral potential

Would recommend vendor to a colleague
• No. 3 in Customer satisfaction
Source: CMP 2002 EDA Study for all companies
© Copyright 2002 Nassda Corporation
4
Nassda Verification & Analysis Space
System
Design
Synthesis &
Circuit Design
Pre-Layout
Verification
HSIM
Physical
Design
Post-Layout
Verification & Analysis
HSIM
HSIM
Nanometer Effects
CRITIC
HSIM
HSIM
LEXSIM
HSIM
LEXSIM
Tapeout to
Manufacture
High Perf. Analog &
SoC
ASIC COT Mixed-Signal
© Copyright 2002 Nassda Corporation
Memory
5
Rapid Growth for Nanometer-Scale ICs
• New challenges
Bigger circuit size
 Parasitic effects
(interconnect delay,
noise, IR drop,
ground bounce,
electromigration)

• Nassda products
analyze complex
circuits with
detailed parasitic
effects
180nm
130nm or below
100
90
80
70
60
50
40
30
20
10
0
1999
2000
2001
2002E 2003E 2004E
Source : Company data, Dataquest Oct. 2002
© Copyright 2002 Nassda Corporation
6
A Mixed-Signal IC Example
How to design
and verify a
nanometer
mixed-signal
IC with
several tens
of million
transistors ?
MPEG-4 decoder with audio & video processing,
PLL, multiplexer, peripheral I/F & on-chip DRAM
© Copyright 2002 Nassda Corporation
7
Nassda’s HSIM Solution
Nassda meets the verification challenge
with full-chip circuit simulation and analysis
• High capacity (> 1 billion transistors)
• High speed with accuracy
• Analog, mixed-signal and memory
• Analysis focus
Timing
 Power

Parasitic effects
 Signal integrity

© Copyright 2002 Nassda Corporation
8
Circuit Simulation Technology Evolution
1st Generation (SPICE)
2nd Generation (Fast SPICE)
Memory Usage
Memory Usage
100M
Bytes
Next Generation (HSIM)
Memory Usage
1G Bytes
100K elements
2M elements
512M Bytes
300M elements
CPU Time
Circuit Size
100
hrs
Circuit Size
CPU Time
Circuit Size
CPU Time
20 hrs
100K elements
2M elements
2 hrs
300M elements
Circuit Size
Circuit Size
© Copyright 2002 Nassda Corporation
Circuit Size
9
Nassda’s Technology
• Hierarchical circuit database
• Hierarchical simulation engine
• Advanced analog & mixed-signal algorithms
• Efficient nanometer effects solver
• Very latest MOS, Bipolar, SOI models
• Innovative parasitic reduction algorithms
© Copyright 2002 Nassda Corporation
10
HSIM Simulation Flow
Device
Models
Spice
Netlists
VCD
Stimulus
HSIM
Run
Log
Measure
Results
Timing
Check
Power
Check
© Copyright 2002 Nassda Corporation
11
HSIM Capacity & Performance Examples
Circuit Type
(#MOS, #R,#C,#L)
Total
Elements
Memory
Usage
CPU
Time (hrs)
Memory A
(159M, 159M, 155M,0)
473M
775MB
1.65
Memory B
(3.1M, 5.4M, 4.5M, 88)
13M
195MB
0.69
D/A
(9K,65K,47K,0)
121K
42MB
1.11
PLL
(2K, 8K, 23K, 0)
51K
15MB
0.21
525K
111MB
0.37
Analog
(119K, 175K, 232K,0)
HSIM efficiently analyzes a wide-range of designs
© Copyright 2002 Nassda Corporation
12
Mitsubishi 512 Mb DRAM
• Netlist with over 2 billion elements
• Simulate 4 Rd / Wr cycles in 6 hours on
32-bit workstation
• Largest real circuit ever simulated
• “HSIM has demonstrated many times that it has the speed,
accuracy, and capacity for our most sophisticated and
complex memory designs. Because HSIM has these
unique capabilities, we are able to simulate an entire
512Mb DRAM at the transistor-level with all memory cells
in place. This results in Mitsubishi delivering even higherquality designs with better yield to its customers.”
Hisaharu Miwa
Manager of EDA Engineering
Mitsubishi Electric
© Copyright 2002 Nassda Corporation
13
Pre-Layout Speed Benchmarks
Vendor A
Runtime
HSIM
Not possible,
exceed capacity
MOS:
Video Chip
1.1M
Network Proc. 1 Network Proc. 2
1.1M
50M
© Copyright 2002 Nassda Corporation
Not possible,
couldn’t complete
PLL
1.8K
Mixed Signal
300K
14
Post-Layout Speed Benchmarks
Vendor B
Vendor A
HSIM
Runtime
Did not finish after 14 days
Not possible,
exceed capacity
A/D
MOS:
R:
C:
10k
50k
200k
D/A
5K
30K
150K
PLL
1.5K
10K
7K
DRAM 1
120K
250K
200K
© Copyright 2002 Nassda Corporation
DRAM 2
SRAM
150K
25K
100K
200K
700K
20K
15
Mixed-Signal Success
© Copyright Nassda Corporation
Success at Silicon Access Networks
•
20Gbps iFlow Chipset



•
0.13u TSMC analog/mixed signal
designs
GHz Ser/Des plus many analog
blocks (e.g. PLLs) and
megabytes of memory
Performance and time-to-market
critical
HSIM-based verification
methodology allowed Silicon
Access to…



Perform critical analog
simulations - PLL power up,
synchronization operations, and
jitter, and SerDes clock recovery
Reduce standby power through
leakage checks
Have a post-layout timing
simulator for all circuits
© Copyright 2002 Nassda Corporation
17
Success at Accelerant Networks
• 10Gbps Network Transceiver




130K-transistor analog/mixed signal
design, .25u TSMC
Many Analog Blocks (PLL, DLL, A/D,
etc.)
Several Thousand Cycles of simulation
required for each block
Existing simulation solution would have
taken weeks (if it completed at all)
• HSIM-based verification
methodology allowed Accelerant
Networks to…




Verify critical timing performance (PLL
settling, clock skew, etc.)
Simulate 8uS of Full Chip performance
Verify post-layout extracted RLC
Drop a cumbersome mixed-mode
approach (Verilog/Spice)
© Copyright 2002 Nassda Corporation
18
Memory and Analog Customer Success
• "We used HSIM extensively and successfully for performing full chip
verification of Saifun's non-volatile memory designs. We got an
excellent support starting from the business front, continuing with a
very good response time to our questions and finally with on-site
support. I would like to thank you at Nassda for helping us with our
latest tapeouts. These projects are very important to Saifun's future."
Ronen Moldovan
CAD Manager
Saifun
• “We are working on some of the largest analog integrated circuits in
the world. The HSIM tool has enabled us to perform simulations that
were simply not possible with any other simulation tool despite the
amount of hardware dedicated to the task. We were also very
impressed with your sales staff and support."
David Madajian
Analog IC Design Manager
Raytheon
© Copyright 2002 Nassda Corporation
19
HSIM Version 2.0
• Power leakage analysis
• CircuitCheck option
• New SPICE analyses
• Cadence Analog Artist integration
• Latest MOS & bipolar models
© Copyright 2002 Nassda Corporation
20
CircuitCheck™ Option
• Static crosstalk and delay analysis at
post-layout stage
• Dynamic operations checks

e.g. Vgs > limit && Vds > value
• Netlist, model, parameter checks

Bad values, connections
• Interactive traceback

What caused this signal to change?
• Save days to weeks of debug time
© Copyright 2002 Nassda Corporation
21
LEXSIM: Full-chip Verification of
Power-Net IR Drop
© Copyright Nassda Corporation
Why Power Net IR Drop Analysis?
• LVS-clean doesn’t mean complete, correct design


Undersized power net structures
Missing via, via array, or strapping
• Finding excessive IR drop not sufficient
IR drop induced change in
path delay (%)

Determining true performance is critical
• Delta path delay
(%)
40%

30%

0.13µ
• If you have
20%

10%
1.0V
Post-layout
Determine
influence of IR drop

0.25µ
1.2V
1.5V
1.8V
2.0V
2.5V
3.0V
Fine-line process
Low VDD system
• Probable design
failure
3.3V
© Copyright 2002 Nassda Corporation
23
LEXSIM Post-Layout Tool
• Full-chip analysis
• Power net effects
IR drop, and influence
on design timing
 Ground bounce (with
inductors)

• Signal net effects
Crosstalk-induced
noise and delay
 Glitch power due to
coupling capacitors

© Copyright 2002 Nassda Corporation
24
LEXSIM Technology Foundation
• Production proven simulation engine
• Power net reduction
 Efficient
disk storage (save/restore)
• Parasitic annotation to pre-layout
 Signal
nets (ground and coupling cap)
 Power nets
 Enables high-speed, high-capacity
simulation
© Copyright 2002 Nassda Corporation
25
LEXSIM Benchmark Results
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
HSIM
S. Co. HF
V. Co. (P&S)
LEXSIM
B. Co. (P)
M. Co. 64M
(4)
M. Co. 64M
(3)
B Co. (P&S)
© Copyright 2002 Nassda Corporation
26
Normalised transient analysis time
80.0
LEXSIM Success at Matsushita
“Being able to more accurately predict the behavior
of our large embedded memory designs requires
the inclusion of the effect of IR drops in the power
networks. With smaller nanometer geometries and
finer metallization, in combination with the higher
currents at lower VDDs, we see the need for
detailed power-net analysis to prevent possible
dynamic IR drop caused design failures. LEXSIM
has demonstrated the ability to simulate our fullchip at the post-layout stage including both signalnet and power-net parasitics. We expect to see
reduced design turns and faster time-to-volume by
using LEXSIM.”
Hiroyuki Tsujikawa, Manager,
Matsushita’s EDA Technology Development Group
© Copyright 2002 Nassda Corporation
27
CRITIC:
Critical Timing Analyzer for Digital ICs
© Copyright Nassda Corporation
Nanometer Analysis for Digital ICs
• Critical timing analyzer for post-layout
verification of the clock networks and
critical paths in cell-based designs
• Augments gate-level static timing
analysis
• For aggressive designs >300 MHz or
in 130nm
• Automated analysis increases
confidence in final timing signoff
• Nassda’s circuit simulation technology
gives best-in-class performance,
precision, capacity
© Copyright 2002 Nassda Corporation
29
General CRITIC Flow
Current flow
RTL-to-GDSII
environment
RTL
Design
Synthesis,
P&R
Extraction
DSPF or
SPEF
Gate-level
STA
Cell
library
Verilog
netlist
CRITIC
Parasitics
clock net
simulation
clock delay
report
Critical
Paths
SDF
critical path
simulation
© Copyright 2002 Nassda Corporation
path delay
report
30
Example Critical Path Analysis Result
1280 Paths Comparison
(sorted by decreasing delays)
40.00%
30.00%
Timing
Difference
20.00%
10.00%
0.00%
-10.00%
Data Paths
• 10-30% difference compared to static
timing analysis means possible chip failure
• CRITIC identifies all cell & path segments
contributing to error
© Copyright 2002 Nassda Corporation
31
Enabling Nanometer Silicon Success
For more information on why over 150
companies rely on Nassda for verification and
analysis of their complex analog, mixed
signal, memory, system-on-chip and high
performance digital designs, please contact:
Nassda Corporation
2975 Scott Blvd., Suite 110
Santa Clara, CA 95054
408-562-9168
[email protected]
www.nassda.com
© Copyright 2002 Nassda Corporation
32