Transcript 3D technologies at Leti: Application to high energy

3D technologies at Leti:
Application to high energy
CMOS sensors
Gabriel Parès
CEA LETI – Open 3D
Workshop INFIERI
21th of January, 2014
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Outline
 Introduction: 3D at Leti
 Silicon interposers
 Open3D and Medipix CMOS sensor application
 Perspectives and conclusions
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Introduction : Why do we need 3D Integration ?
 To solve the following issues :
 Form factor decrease :
 X & Y axis
 Z axis
 Performances improvement
 Decrease R, C, signal delay
 Increase device bandwidth
 Decrease power consumption
 Heterogeneous integration
 Integration of heterogeneous components
in the same system
 Cost decrease
 Si surface decrease
 Reuse of existing Packaging,
BEOL & FEOL lines
Interposer / substrate
passives
Memory
Logic
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 3
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French R&D institute in
microelectronics &
nanotechnologies from
About CEA-LETI
1,700 researchers
Over 2,200 patents
250 M€ annual budget
50 start-ups
& 365 industrial partners
Grenoble, France
 ~100 people working on 3D IC and 3D Packaging
 Full 200mm & 300mm 3D capabilities
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LETI - Open 3D™ organization
CEA
LETI
DCOS
Silicon components
DTSI
Silicon platform
DTBS
Biology and Health
DOPT
Imaging
DACLE
Design
3 Sections
 SCME Components
 SCMS MEMS-NEMS
 S3D 3D Integration
4 Laboratories

LSA

LP3D 3D packaging


LECA Adv. die stacking
LCFC Reliability / characterization
Substrate
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Outline
 Introduction: 3D at Leti
 Silicon interposers
 Coarse interposers
 High density interposers
 Thin silicon mechanical management
 Open3D and Medipix CMOS sensor application
 Perspectives and conclusions
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Heterogeneous vs high density history
Silicon 3DIC
Side-by-side e-WLB
Density
e-WLB
high
Package-on-Package
Silicon interposer
WLP +IPD modules
Fan-in flipchip
medium
Embedded 3D-SiP
Wirebond stack
FC-BGA
WB-BGA
Fan-in
2 chips FC
low
low
medium
2D-SiP
Heterogenous
high
functionalities
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2 ways of thinking “silicon interposer”
Coarse Interposers
 Heterogeneous integration


Medium I/Os count
High flexibility
High Density Interposer
3µm
15µm
M1
M5
 IC integration


Large I/Os count
Specific
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2,5D: A “generic” solution?
High performance
computing
High-end servers
FPGA
Mobile
3D Imaging
From Fujitsu
Passive /active
-
- 3D stack on interposer
- ~150 - 200W
-
products
4 levels of BE
20 Watts
28 Gbps
-
PoP still there!!
Supply chain
5-10 Watts
12 - 50 Gbps
-
3D technology for
tracker
<40µm pixels
Read out circuit
at the back
Ultra fine routing
at the interposer
backside
Under developement
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2000 - 2013: Leti 3D ‘generic’ technology toolbox
1 active layer
Face to Face
Face to back
Die to Die
Die to Substrate
Through
Silicon Via
Handling
Solder balls
Wire Bonding
TSV First
Solder balls
Copper Pillars
µinserts
µtubes
Cu-Cu
3 level stack
Die Placement
WL Molding
Temp. Bonding
(slide off)
High throuput
P&P
Thick Polymer
molding
TSV Middle
& BS AR10
Temp Bonding
(Zonebond)
High precision
P&P
Thin Polymer
molding
Copper pillar
TSV Last
AR1
Temp. bonding
(Peeling)
Self Assembly
Thin Oxide
planarization
DTW Cu-Cu
TSV Last
AR2
Permanent
bonding
Wafer
To Wafer
WLUF
TSV Last
AR3
Classic
Underfill
TSV Last
High density
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Coarse interposer : the TSV last background

LETI transfer to ST Micro (2005  2008)
 CMOS Imager sensor application
 Through Silicon Via via-last Aspect Ratio 1 : 1
 Cu liner
 Production mode since 2009
 300 mm production line @ STM Crolles
Vias last process
FEOL - CMOS
BEOL
Bonding perm. or
Temporary
(C2W or W2W)
Via formation
Back Side process
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Today coarse interposers developments (2010 -2014):
Passive interposers
Medical applications
radar, military, space
Mmw platform:
High perf. Passives
(Capa 1µf/mm2)
Active interposers
Consumers
Fondamental physics
Power amplifier (PA) 4G
with TSV:
Particles detectors:
X-rays/particles dead
zone free detectors
3x3 mm2
130nm SOI CMOS
60µm TSV
75µm TSV
40% size decrease vs. organic
6,5 x 6,5 mm2
60µm TSV
14x17mm2 detector,
Medipix 130nm CMOS
60µm TSV
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High density interposer roadmap
Drivers: higher density, more I/O’s, more computing
Lithography
Stitching
L/W 0.1um
Active
interposer
100k I/Os
2,5D
Performance

65nm/65nm
45x45mm
60k I/Os
TSV-middle 5µm
35x35mm
TSV 10x100µm
L/W 0.5um
TSV-middle
10µm
3D Stepper
Investment
25x25mm
2013
2014
2015
3D
2016
Year /
size
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Challenge: warpage control of large interposer
Example of flip-chip assembly of thinned FEI4 (ATLAS)
sensor
FEI4
7.3 x 10.9 mm2
20 x 18.9 mm2
Radiation hard  very thick BEOL
 Huge stress to control
From Fraunhofer IZM , T. Fritzsch ACES 2011
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Protocol for stress compensation at Leti
 Backside compensation layer deposition
Material development (Young modulus, CTE)
Wafer & die level stress optimization
30x30 mm2 test dies and FEI4 wafers tests on going
Glasgow
University
Backside compensation layer
Materials tuning & model
Wafer level integration
Die level bow monitoring
SiN
Topography and Deformation Measurement (TDM)
J. Charbonnier et al. EMPC 2013
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Outline
 Introduction: 3D at Leti
 Silicon interposers
 Open3D and Medipix CMOS sensor application
 Perspectives and conclusions
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 16
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Introduction to Open 3D™ platform
 The concept :
 Open 3D™ is a 3D technology offer, targeting industrial & academic customers
 Key features :
 Process of existing Si wafers: no re-design required
 Light R&D investment : based on mature 3D technologies
 Short cycle time
 200 mm & 300 mm (2014)
 Global offer from 3D design to component final packaging
 Possibility to make proof-of-concept , prototyping & small volume production
 Open 3D customer’s typology :




Laboratories, universities and international Institutions
Fabless
“Niche” markets manufacturers & integrators
IDM
Projects already
started with :
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Technological OPEN3DTM offer overview


Wafers (bottom and/or top dies) provided by costumer
Technological modules implemented by OPEN3DTM :
 Through Silicon via (TSV)
 Redistribution layer (RDL)
 Under Bump Metallization (UBM)
 Interconnections
 Components stacking
 Packaging with partner collaboration
OPEN3DTM inputs
Top dies wafer (provided
by costumer)
Front side UBM
Costumer inputs
Micro-bumps
Micro pillars
wafer provided by
costumer
TSV
Passivation
RDL
Back side UBM
Bumps
Pillars
BGA or package
(provided by costumer
or OPEN3D)
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Technological OPEN3DTM offer overview
Wafer reception at LETI
Design & Layout
3D Technology implementation
TSV
Open 3D™ wafer service
Packaging
Interconnections
 need identification
 specifications on 3D
Metalization
Electrical Tests
100,00%
90,00%
80,00%
P02
P03
P05
P06
P07
P08
P09
P10
P11
P12
70,00%
60,00%
50,00%
40,00%
30,00%
Components stacking
20,00%
10,00%
0,00%
0,00
0,50
1,00
1,50
2,00
2,50
3,00
3,50
4,00
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X-Rays/Particles hybrid pixel detector application
CERN – LETI Project summary
 Product : X-Ray hybrid pixel detector for medical applications
 TSV last made in MEDIPIX wafers
 Suppression of lateral wire bonding
 Buttable sensor assembly
CMOS pixel sensor
ROIC
Medipix specifications
Design
Test structures
Wafer diameter: 200mm
Wafer thickness: ~725um
IC Technology: 130 nm / IBM
Top Surface: Al + Nitride
Chip size : 14100 x 17300 µm
TSV per chip: ~100
Process Flow
Wafer view
Single chip
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Technological and electrical results
 New lot with MEDIPIX RX running at LETI
TSV Medipix3 results - 2012
Technology
RDL Cu 7 µm
Back side UBM
Medipix wafer after front
side UBM
Accoustic image of
the bonding interface
TSV
60µm
x120µm
Thin wafer
debonded on tape
Contact UBM
TSV:
Electrical Tests
Functionnal tests on ASICS
P01-Résistance cum ulée Chaine de 2 TSV (VSS)
100
90
80
70
%
60
50
Test RDL
40
Test Final
2 TSV chain resistance
30
20
10
0
5. 20E -01
5. 40E -01
5. 60E -01
5. 80E -01
Ohm s
6. 00E -01
6. 20E -01
6. 40E -01
TSV Last for Hybrid Pixel Detectors: Application to Particle Physics and Imaging Experiments
D. Henry(1), J. Alozy(2), A. Berthelot(1), R. Cuchet(1), C. Chantre(1), M. Campbell(2) ECTC 2013
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On-Board Integration by Advacam
 One TSV processed ROIC wafer diced and “good” chip
candidates selected
 Sn-Pb µ-solder balls were processed on Edgeless Sensor
 μ-Solder bumping successfully done
Pixel pad on ROC
(after debonding of previous trials)
Sensor with Sn-Pb solder bumps
After reflow process
SEM images courtesy of Advacam
First Edgeless-TSV assembly
5 were provided to CERN in October 2013
Courtesy of Jerome ALOZY - CERN
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Chip and assemblies mounting by CERN
 BGA pads on the redistribution layer (back side of the chip) have been
populated manually with low temperature solder balls
 Chip soldering on the board by reflow in an oven
PCB BGA footprint
Bare chip with solder spheres
57Bi42Sn1Ag/Indalloy #282
First trial with a bare Medipix 3.1 chip
100 solder spheres of 0.635mm (after first reflow to attach them)
Courtesy of Jerome ALOZY - CERN
Courtesy of S. Kaufmann
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First functional test
 Conditions
 X-Ray chamber 35kV, 1mA
 Hybrid Pixel Detector was positioned in front of the X-Ray beam
 A biological sample (fish) placed before the detector
 Results
 First image was successful
 The sensor bias current was high when applied through TSV compared to direct connection
to sensor : possible reason are TSV insulation, leakage in assembly stack (humidity, bismuth
solder balls)
First image obtained with a TSV processed
hybrid pixel detector (flat field corrected)
Courtesy of Jerome ALOZY - CERN
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 24
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Outline
 Introduction: 3D at Leti
 Silicon interposers
 Open3D and Medipix CMOS sensor application
 Perspectives and conclusions
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 25
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Open 3D™ : Technological roadmap
Technologies
Available for :
Fine pitch interco
Proof of concept
Available for :
TSV last shrinking
TSV Middle
Damascene RDL
Proof of
concept
Prototyping
Available for :
TSV Last AR 3:1
Stacking D2W
 Low temp Interco
TSV Last AR 1:1 & 2:1
µbumps / µpillars
Bumps / pillars
UBM
Prototyping
Proof of
concept
Prototyping
2013
Prototyping
Small volume
production
Small volume production
2014
2015
2016
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 26
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What the next step in 3D?
 CMOS images sensor… once again
 The market is ready and 3D WLP supply chains exist
 3D stack of 2 partitioned dies
 65nm processor reported below a 130nm image sensor
ANR 3D-IDEAS project - 2012
From, P. Coudrain et al. ECTC 2013
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3D imagers requires high density

Step 1 : 2-layer 3D imager (Back Side imager stacked on CMOS)

Collaboration with ST
Leti objective : demonstration in 2014, technology in production in 2016-2017
transistors
Back Side Imager
Hybrid Cu and SiO2, face-to-face, bonding
Pitch 5-10µm
CMOS
TSV (10µmx80µm), pitch 40µm
Solder bumps, connection to board (or interposer)

Step 2 : 3-layer 3D imager : detector on 2 CMOS layers

Leti objective : demonstration in 2015-2016, technology in production in 2018-2019
Detector
Consortium to be defined
Connection to detector, pitch 40µm
transistors
Hybrid Cu and SiO2, face-to-face,
bonding, Pitch 5-10µm
Solder bumps, connection to board,
interposer or 3D package
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 28
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Key technology: Cu and SiO2 hybrid bonding
 Bonding technology feasibility demonstrated
 >90% yield obtained with daisy Chains with 30,000 3x3µm² Cu contacts
 Contact resistance : 2,5 mΩ
Optical top view
0.5 µm
thick line
Acoustic image of bonding
standard deviation σ ~ 1.2%
Resistance (Ω)
Contact chain SEM cross section
Full characterization of Cu/Cu direct bonding for 3D integration, Rachid Taibi,
Léa Di Ciocciob et al., ECTC2010
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 29
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Key technologies: ultra fine TSV
High density 3D Flow:
Wafer to Wafer & Die to Wafer stacking
 3µm diameter TSV via-last after bonding
 Cu-Cu direct bonding
TSV last after bonding
Permanent bonding W2W
Ultra fine pitch TSV
3µm
15µm
M1
15µm
M5
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 30
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Main conclusions
 Coarse and fine interposers offer already some credible alternative
 Seen more like an evolution of packaging
 Some benefits in ‘niche’ applications: medical, space, fundamental physics.
 Strong challenges on the size of the modules
 LETI is well positioned to offer 3D solutions for low volume applications




15 years of development work
A complete toolbox of process bricks
200/300 mm capabilities
Open 3D™ platform to address customer requests
 3D integration for image sensors has long been introduced and will
continue to be a main driving application
 CMOS sensors, MEDIPIX and many other applications will continue benefiting from 3D
 With higher density of integration as the next frontier
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 31
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Main acknowlegements for this presentation:
 Y. Lamy
 D. Henry
 G. Simon
 P. Leduc
 S. Chéramy
 JC Souriau
 Jf Teissier & E. Rouchouze
LETI Optronic Department’s colleagues
Shinko, IPDIA, ST, LETI’s partners…
Thank you for
attention
[email protected]
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 32
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How to work with Open 3D™

Simple process for customer
Possible access to layout & Wafers through CMP
Tech. Specifications /
planning
Device layout
Wafers
PO
Open 3D™ TechBox
Design &
Layout
3D Technology
Tests
Innovative product for your market
Markets
3D Packaging
Technical contact :
[email protected]
[email protected]
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 33
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TSV-last insight
TSV DRM & schematic
Top metal
 Wafer size :
200 & 300 mm
 TSV type :
via last / Cu liner
 Minimum pitch :
80 µm (for 40µm TSV)
 TSV diameter :
40 to 100 µm
 Aspect Ratio (AR) :
from 1:1 to 3:1
Metal 1
Dielectric
liner
TSV Metal liner
RDL
Passivation
TSV morphological & electrical results
AR 1:1
AR 2:1
AR 3:1
TSV characteristics
TSV geometry
R (mW)
C (pF)
Elec. Yield
Insul. (MW)
I leak (A)
TSV60 / 80
15.1
0.57
100 %
> 100
-
TSV60 / 120
19.1
0.82
100 %
> 100
1.3 10-9 @ 10V
3.1 10-9 @ 50V
TSV40 / 80
20.1
0.46
> 99%
> 100
-
TSV40 / 120
30.4
0.63
> 99%
> 100
7.4 10-9
100,00%
90,00%
80,00%
Electrical tests
P02
P03
P05
P06
P07
P08
P09
P10
P11
P12
70,00%
60,00%
50,00%
results
40,00%
30,00%
20,00%
10,00%
0,00%
0,00
0,50
1,00
1,50
2,00
2,50
3,00
3,50
4,00
Gabriel Parès - 3D integration – Workshop INFIERI 2014 Jan. 21, 2014 | 34
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