Transcript 20120323_LitRev_SIMD_Intel

Literature Review
A 280mV-to-1.1V 256b Reconfigurable SIMD
Vector Permutation Engine with 2-D Shuffle
in 22nm CMOS [ISSCC ’12]
Fang-Li Yuan
Advisor: Prof. Dejan Marković
03/23/2012
IC Design Challenges: 1980s – Present
 Session 1.4: Sustainability in Silicon & System Development
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1980s: Design productivity
1990s: Power dissipation
2000s: Leakage power
2010s:
Energy Efficiency
Moore’s Law continues to provide more transistors
Power budgets limit our ability to use them
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Intel’s Solutions – From Transistors to Circuits
2012 ISSCC
2007 ISSCC
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Near-Vth Computing: Great for Energy Efficiency
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IA-32: 1st NTV Processor in 32nm CMOS
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NTV Circuits Gain 7x Efficiency in VPFP Mult-Add
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1st NTV SIMD Engine in 22nm Tri-Gate Technology
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System-Level Overview
32 32×8b 3R1W RF: 4~32-way,
8/16/32/64b Vertical Perm.
256b, byte-wise, any-to-any
Crossbar: Horizontal Perm.
Goal:
(1) Provide flexiblity
(2) Improve Vmin
(3) Reduce power
(4) Lower PVT var.
Results:
585 GOPS/W @280mV
(9x higher than 1.1V)
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Example: 64b 4x4 Matrix Transpose
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RF with PVT-tolerant Techniques & Vector FFs
Clockless static reads eliminate
keeper contention in dynamic BLs
Byte-wise enable-signal gating
reduce 49% of switching power
Shared P/N on virtual supplies limits
strength of cross-coupled INVs
Vector flip-flops w/ shared
local min-sized clock INVs
average the variation
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250mV Vmin Reduction Across PVT Variations
250 mV
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Vector FFs Reduce Hold-Time Violations @ Low V
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ULVS LS, & Interleaved Folded Crossbar Layout
Vector mux averages variation
effect of min-sized devices by
sharing transistors across gates
Folded layout: 50%
reduction of wiring
Interleaved layout:
50% lower coupling
Decouples CVSL stage from o/p
driver & contention devices: 20~32%
lower power, 125mV improved Vmin
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ULVS Improves Vmin by 125mV
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RF and Logic Co-optimization: Iso-Vmin
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Measured Performance
RF: 227mW, 2.5GHz @1.1V
Xbar: 69mW, 2.9GHz @1.1V
585 GOPS/W @0.26V
(9x higher than 0.9V)
RF: 106mW, 1.8GHz @0.9V
Xbar: 36mW, 2.3GHz @0.9V
RF: 109μW, 16.8MHz @0.28V
Xbar: 19μW, 10MHz @0.24V
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Conclusions
 NTV computing is energy efficient but sensitive to PVT variation
 Static ckts (e.g. RF read): better than dynamic ckts @ NTV
 Shared P/N DETG writes improve Vmin across PVT variations
 Vector FF/Mux share transistors across gates, averaging variation
 ULVS LS interrupts contention devices, improving Vmin & power
 Byte-wise enable-signal gating reduces power
 Folded layout has 50% reduction in critical wiring length
 Interleaved, opposite-direction data wires achieve 50% lower
line-to-line coupling, improving SI & delay
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