Transcript Lecture 1 - Introduction and Organizational Issues

ECE 448
FPGA and ASIC Design
with VHDL
Spring 2010
ECE 448 Team
Course Instructor:
Kris Gaj
[email protected]
Lab Instructors (TAs):
Monday & Tuesday section:
Jeremy Kelly
jeremy.a.kelly (at) gmail.com
Wednesday section:
John Pham
jhnphm (at) gmail.com
Thursday section:
Brian Loop
bdloop (at) gmail.com
ECE 448 Team – Division of Tasks
Course Instructor – Primary Responsibilities
- Lectures
- Preparing and grading exams and quizzes
- Coordination of work on development
of new experiments
- Instructions for the lab experiments
- Coordination of work done by the TAs
- Enforcing consistent policies and grading standards
- Mid-semester student satisfaction survey
- Resolving conflicts and providing feedback to the TAs
- Holding office hours
ECE 448 Team – Division of Tasks
Lab Instructors (TAs) – Primary Responsibilities
- Teaching hands-on sessions on how to use software,
hardware and testing equipment needed for experiments
- Introductions to the lab experiments
- Grading student demonstrations and reports
- Holding office hours
- Development and testing of new lab experiments
ECE 448 Section Assignment Rules
• You are welcome to attend any of the
multiple office hour sessions
• Please attend the class meetings of the other section only
in case of emergency and give preference in access
to the lab computers to the students attending
their own section
• All experiment demonstrations need to be done
in the presence of your TA, and can be
done exclusively during the class time of your section
Course Hours
Lecture:
Monday, Wednesday
5:55-7:10 PM, Lecture Hall, room 2
Lab Sessions:
Monday, Tuesday, Wednesday, Thursday
7:20-10:00 PM, The Nguyen Engineering Bldg., room 3208
There will be no lab meetings in the first week of classes!!!
Tentative Office Hours
Saturday, 12:00-1:00 PM, John Pham, Engineering 3208
Monday,
7:30-8:30 PM, Kris Gaj, Engineering 3225
Monday, 10:00-11:00 PM, Jeremy Kelly, Engineering 3208
Tuesday,
6:00-7:10 PM, Jeremy Kelly, Engineering 3208
Wednesday, 4:30-5:30 PM, Kris Gaj, Engineering 3225
Wednesday, 7:30-8:30 PM, Brian Loop, Engineering 3204
Lab Access Rules and Behavior Code
Please refer to
Computer Engineering Lab website
and in particular to
Access rules & behavior code
Grading criteria
First part of the semester (before the Spring break)
Lab experiments - Part I
20%
Quizzes & homework: 5%
Midterm exam for the lecture: 10%
Midterm exam for the lab:
15%
Second part of the semester (after the Spring break)
Lab experiments - Part II
20%
Quizzes & homework: 5%
Final exam
25%
Required Textbook
Pong P. Chu,
FPGA Prototyping by VHDL Examples: Xilinx
Spartan-3 Version,
Wiley-Interscience, 2008.
Recommended Textbook
current ECE 331/332 book
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL
Design, McGraw-Hill, 3rd or 2nd Edition
Undergraduate Computer
Engineering Courses
ECE 331
CS 112
C
C
C
CS 211
C
ECE 332
C
C
ECE 445
ECE 448
C
CS 222
ECE 447
ECE 492
BS EE
ECE 493
CS 262
C
CS 367
Color code:
BS CpE
ECE 448, FPGA and ASIC Design with VHDL
Topics
VHDL:
- writing synthesizable RTL level code in VHDL
- writing test benches
FPGAs:
- architecture of FPGA devices
- tools for the computer-aided design with FPGAs
- current FPGA families & future trends
High-level ASIC Design:
- standard cell implementation approach
- logic synthesis tools
- differences between FPGA & standard-cell ASIC design flow
Applications:
- basics of computer arithmetic
- applications from communications, cryptography,
digital signal processing, bioengineering, etc.
Platforms:
- FPGA boards
- microprocessor board–FPGA board interfaces
- reconfigurable computers
New trends:
- using high-level programming languages to design hardware
- microprocessors embedded in FPGAs
Tasks of the course
Advanced
course on digital
system design
with VHDL
Comprehensive
introduction to
FPGA &
front-end ASIC
technology
- writing VHDL code
for synthesis
- design using
finite state machines
and algorithmic state
machines
- testbenches
- hardware:
Xilinx FPGAs,
Library of standard
ASIC cells
- software:
VHDL simulators
Synthesis tools
Xilinx ISE
Testing
equipment
- oscilloscopes
- logic analyzer
VHDL for Specification
VHDL for Simulation
VHDL for Synthesis
Levels of design description
Algorithmic level
Register Transfer Level
Logic (gate) level
Circuit (transistor) level
Physical (layout) level
Level of description
most suitable for synthesis
Register Transfer Level (RTL)
Design Description
Combinational
Logic
Registers
Combinational
Logic
…
VHDL Design Styles
VHDL Design
Styles
• Testbenches
dataflow
Concurrent
statements
structural
Components and
interconnects
behavioral
Sequential statements
• Registers, counters, etc.
• State machines
Subset most suitable for synthesis
Testbenches
Testbench Environment
TB Processes
Generating
Stimuli All DUT Inputs
Design Under Test
(DUT)
Stimuli
Simulated Outputs
World of Integrated Circuits
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
PLD
PAL
PLA
User
Programmable
FPGA
PML
LUT
(Look-Up Table)
MUX
Gates
What is an FPGA?
Configurable
Logic
Blocks
Block RAMs
Block RAMs
I/O
Blocks
Block
RAMs
Two competing implementation
approaches
ASIC
Application Specific
Integrated Circuit
• designed all the way
from behavioral description
to physical layout
• designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
FPGA
Field Programmable
Gate Array
• no physical layout design;
design ends with
a bitstream used
to configure a device
• bought off the shelf
and reconfigured by
designers themselves
FPGAs vs. ASICs
ASICs
FPGAs
Off-the-shelf
High performance
Low development costs
Low power
Short time to the market
Low cost (but only
in high volumes)
Reconfigurability
FPGA Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..
Specification (Lab Experiments)
On-paper hardware design
(Block diagram & ASM chart)
VHDL description (Your Source Files)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Functional simulation
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Synthesis
Post-synthesis simulation
FPGA Design process (2)
Implementation
Timing simulation
Configuration
On chip testing
Simulation Tools
FPGA Synthesis Tools
Logic Synthesis
VHDL description
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;
Circuit netlist
FPGA Implementation
• After synthesis the entire implementation
process is performed by FPGA vendor tools
Design Process control from Active-HDL
Top Level ASIC Digital Design Flow
Design Inception
RTL Design
Synthesis
Macro Development
Place + Route
Physical Verification
Design Complete
ASIC Simulation Tools
ASIC Synthesis Tools
Xilinx FPGA Tools
Windows
ECE Labs
Aldec Active HDL
Home
Aldec Active HDL
Student Edition
ModelSim Xilinx Edition
Synopsys Synplify Pro
Xilinx XST
Xilinx XST (limited)
Xilinx XST (limited)
Xilinx ISE
Xilinx WebPACK
(limited)
Xilinx WebPACK
(limited)
Digilent Basys2 FPGA Board
Digilent Basys2 FPGA Board
FPGA available on the board
Xilinx Spartan 3E-100, XC3S100E FPGA
• 100,000 equivalent logic
gates
• 960 CLB slices
• 72 kbits of memory in
block RAMs
Block RAMs
Programmable
Configurable Logic
Block slices (CLB slices) Interconnects
Digital system design technologies
coverage in the CpE & EE programs at GMU
Microprocessors
ECE 445
ASICs
FPGAs
Computer
Organization
ECE 431
Digital Circuit Design
ECE 447
Single Chip
Microcomputers
ECE 448
FPGA and ASIC Design with VHDL
ECE 511
Microprocessors
ECE 611
Advanced
Microprocessors
ECE 545
ECE 645
Digital System Design with VHDL
Computer Arithmetic
ECE 586
Digital
Integrated
Circuits
ECE 681
VLSI Design
for ASICs
Why ECE 448 is a challenging course?
• need to “relearn” VHDL
• need to learn new tools
• need to perform practical experiments
• time needed to complete experiments
ECE 448: Spring 2006
Student Survey Summary
Difficulties
• finding time to do the labs - 15
• learning VHDL – 2
• getting used to software – 1
Average time spent per one experiment
9
8
7
6
5
4
3
2
1
0
2
6 8 10
15
20
24
30 32
48
Self-evaluation
3 – better than
expected
8 – worse than
expected
16 – as well as
expected
Why is this course worth taking?
• VHDL for synthesis:
one of the most sought-after skills
• knowledge of state-of-the-art tools used in the industry
• knowledge of the modern FPGA & ASIC technologies
• knowledge of state-of-the-art testing equipment
• design portfolio that can be used during job interviews
• unique knowledge and practical skills that make you
competitive on the job market