MOSFET Theory - Carleton University
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Transcript MOSFET Theory - Carleton University
SYSTEM
Cell-Based
FPGA
PLD
Gate
Arrays
ASIC
Full-Custom
DECODER
MODULE
Combinational
X
Sequential
R
E
G
LOGIC GATE
Static
M
U
X
D Q
Basic
Dynamic
CIRCUIT
Simple
Complex
Parallel
Connection
CMOS Inverter
Series
Connection
DEVICE
n+
p
n+
Bipolar
Copy Right
August 2002
Maitham Shams
n+
n+
p
MOSFET
n
p
Diode
Dept of Electronics
Carleton University
Ottawa, CANADA
The MOSFET
Metal-Oxide-Semiconductor Field-Effect Transistor
Heavily doped by
implantation or diffusion
Thick Oxide (S2iO2)
Channel stop implant
or field implant
Field
Oxide
Polycrystalline Silicon
or Polysilicon (conductor)
) 2)
Thin Oxide (S2iO
Gate
Gate Oxide
Source
Drain
n+
p+
For insulating
devices from
each other
n+
p-substrate
Body
p+
Lightly doped
Bulk Contact
Unipolar and symmetric device with four terminals of Gate, Source, Drain, and Body
NMOS: n-type Source and Drain, p-type Body connected to ground (GND)
PMOS: p-type Source and Drain, n-type Body connected to power supply (VDD)
© Maitham Shams 2002
CMOS Technology
Polysilicon
Metal
Gate oxide
contact cut
p+
p+
n+
n+
n-well
p-substrate
PMOS
NMOS
Complementary Metal Oxide Silicon Technology combines NMOS and PMOS
High Reliability
High Integration
Density
Adequate Speed
Mainstream IC Technology
in
Foreseeable Future
© Maitham Shams 2002
Low Power
Consumption
Simple Processing
Steps
MOSFET Types and Symbols
D
D
G
G
S
G
S
Analog
Digital
I DS
D
G
B
0
S
With non standard
substrate connection
+V
Tn
S
VGS
G
G
G
S
S
Analog
Digital
VGS
D
D
-VTn
VGS
0
Depletion NMOS
Enhancement NMOS
D
I DS
D
-V Tp
D
0
B
VGS
0
+V
Tp
G
S
With non standard
substrate connection
I DS
Enhancement PMOS
S
I DS
Depletion PMOS
Enhancement mode transistors are normally OFF (non-conducting with zero bias)
Depletion mode transistors are normally ON (conduct with zero bias)
Most CMOS ICs use Enhancement type MOS
© Maitham Shams 2002
MOS Theory of Operation
(S)
Source
VGS
-
(D)
+(G)
Gate
Drain
n+
+
_
+
_ +
n+
_
_ +
+
_
+
Accumulation
0 VGS VT
_
p-type substrate
(B)
Body
G
S
D
n+
_ _ _ _ _ _
n+
Depletion layer
p-type substrate
B
© Maitham Shams 2002
Depletion
VGS VT
VDS 0
Cut-off
(no current)
MOS Operation (Triode Mode)
Inversion Layer
(n-type Channel)
Inversion
G
S
VGS VT
D
n+
_ _ _ _ _ _ _ _ __ _ _
n+
VDS VGS VT
Depletion Layer
p-type substrate
Current Flow
B
Threshold voltage, VT, is the potential difference between gate and
source, VGS, just enough to invert the channel and let the current flow
In triode (also called linear) mode current
flow increases by increasing VGS and VDS
© Maitham Shams 2002
I (VGS VT )VDS
2
VDS
2
MOS Operation (Saturation Mode)
Inversion Layer
(n-type Channel)
S
n+
Pinch-off
G
______
_
_
_
_
_
_
_
_
____
D
VGS VT
n+
Depletion Layer
p-type substrate
Edge of
Saturation
VDS VGS V
B
Saturation
G
S
n+
__ ______
_
_
_
_
_
_
_
_
__
D
n+
VGS VT
VDS VGS VT
Current flow is constant
almost independent of VDS
p-type substrate
I (V V )
GS
T
2
B
© Maitham Shams 2002
The Threshold Voltage
Voltage drop across oxide (function of VSB)
Surface Charge : due to imperfection in
Voltage drop across
the oxide/substrate interface & doping
Depletion region
Implants: to adjust VT by
introducing a small doped
region at oxide/substrate surface
At inversion
Ideal VT
VT = ms - 2F -
QB QSS QI
Cox Cox Cox = VT - ideal + VFB
Work-function
difference between
gate material and Si
= (gate - Si)
= - (Eg/2 + F)
Depletion Layer Charge
Gate-Oxide Capacitance per unit area
COX =
Band gap energy of Si
T2 )5
= (1.16 – 0.704x10-3
T + 1108
© Maitham Shams 2002
OX
tOX
Oxide permittivity
= 3.5 x 10 -13 F/cm
Oxide thickness
~ 20nm (200A)
The Threshold Voltage
Body Effect
1.6 1019 C
Subthreshold Current
is small amount of
current that flows
through the channel
when gate-to-source
potential is below
threshold voltage
Doping Density
2qSi NA
=
COX
refers to an increase in absolute value of
threshold voltage when body is at lower
potential than source in NMOS and higher
potential than source in PMOS transistors
Body Effect
Coefficient
VT = VT0 + ( |-2F + VSB| - |-2F |)
Zero-Bias
VT
What is VT of an NMOS
transistor if VT0 0.75 V,
Zero-Bias QB
QB0 QSS QI
VT0 = ms - 2F - C - C - C
OX
OX
OX
© Maitham Shams 2002
F -0.6 V,
and VSB 5V?
MOS I – V Relations
ID
ID (mA)
VDS = V GS - V T
0.020
VDS = 5V
VGS = 5V
2
Subthreshold
Current
Triode
VGS = 4V
Saturation
1
0.010
VGS = 3V
VGS = 2V
VGS = 1V
0
1
2
3
4
0.0
5
VDS(V)
ID as a function of VDS
VT 1.0
2.0 V
GS
ID as a function of VGS
Channel Length Modulation
Refers to the fact that due to the enlargement of depletion layer on the drain side and,
hence, reduction of channel length, ID slightly increases as VDS increases in saturation
© Maitham Shams 2002
(V)
Simple MOSFET Model
VDS > VGS – VT
Saturation
Square Law:
’ W
ID = k n
( VGS - VT)2(1 + VDS)
L
L
G
D
ID
S
MOS technologies are known
by their Feature Length
(minimum allowable L)
VDS < VGS – VT
Linear
2
V
’
DS
W
ID = k n
{( VGS - VT)VDS }
L
2
Process transconductance parameter
Designers usually change size (usually width)
of transistor to get the right amount of current
Saturation (ON) and cut-off (OFF) are the more
important modes in operation of digital circuits
K nCox
'
n
electron mobility, about 3
n Istimes
larger than hole mobility
© Maitham Shams 2002
MOS Capacitances
CGS
CGD
Gate
Drain
Source
n+
C SB
CGS
G
CGB
Body
p-substrate
B
MOS capacitances are nonlinear functions of voltages
across them
CDB
are oxide capacitances between
gate and channel on the source and drain
sides, respectively
CGD
D
CDB
C SB
n+
MOS parasitic capacitances
govern it’s dynamic
behavior
cGS , cGD
CGB
S
t ox
cGB is a combination of gate-to-channel
and channel-to-body capacitances
cSB and cDB are junction (also called diffusion)
capacitances due to reverse-biased diodes
© Maitham Shams 2002
Gate-Oxide MOS Capacitances
Average Gate Related Capacitances
Operation Region
CGB
CGS
CGD
Cut-Off
CoxWL
0
0
Triode
0
Saturation
0
CoxWL / 2 CoxWL / 2
0
(2 / 3)CoxWL
© Maitham Shams 2002
Junction Capacitance
Cj (fF)
Average value of Cj between
VH and VL
Ceq = Qj / VD = Keq Cj
Keq =
abrupt junction
1.0
- 0m
(VH – VL)(1-m)
0.5
linear junction
x [(0 – VH )1-m – (0 – VL )1-m]
2.0
0.0
0.0
VD (V)
Junction behaves like a
capacitance becomes its
charge depends on the
voltage across it
Cj =
Cj0
(1 – VD / 0)m
© Maitham Shams 2002
Junction capacitance at zero
bias given per unit area
Grading coefficient
0.5 for abrupt junction
0.3 for linear junction
Non-ideal Behaviour of MOSFET
Latch up
Threshold variations
Parasitic Resistances
Subthreshold current
- Power Law for Sub-micron MOS in Saturation
ID = k W(VGS – VT), 1.25
Short Channel Effects:
Velocity Saturation
and
Mobility Degradation
© Maitham Shams 2002
The Threshold Voltage
Example:
VT0 = 0.75 V, = 0.54
2 F = -0.6V, VSB = 5V
VT = 1.6V > 2VT0
© Maitham Shams 2002