Transcript OpAmp

OpAmp (OTA) Design
The design process involves two distinct
activities:
• Architecture Design
– Find an architecture already available and
adapt it to present requirements
– Create a new architecture that can meet
requirements
• Component Design
– Design transistor sizes
– Design compensation network
All op amps used as feedback amplifier:
If not compensated well, closed-loop can be
oscillatory or unstable.
damping ratio z ≈ phase margin PM / 100
Value of z: 1 0.7 0.6 0.5 0.4
Overshoot: 0 5% 10% 16% 25%
0.3
37%
Unit step responses for various z
1.8
z=0.1
1.6
z=0.2
1.4
z=0.3
1.2
z=0.4
z=0.5
z=0.6
1
z=0.7
G(s)= 2n/(s 2+2zns+ 2n)
z=1
0.8
0.6
z=2
0.4
z=5
0.2
0
z=10
0
2
4
6
8
10
nt (radians)
12
14
16
UGF: frequency at which gain = 1 or 0 dB
PM: phase margin = how much the phase is
above critical (-180o) at UGF
Closed-loop is unstable if PM < 0
Bode Diagram
Gm = 18.065 dB (at 1.4145e+009 rad/sec), Pm = 38.171 deg (at 4.2821e+008 rad/sec)
Magnitude (dB)
100
UGF
50
0
-50
0
Phase (deg)
-45
-90
PM
-135
-180
-225
-270
4
10
5
10
6
10
7
10
Frequency (rad/sec)
8
10
9
10
10
10
Two Stage Op Amp Architecture
z
UGF
GM<0
p1
p2
z1
PM<0
UGF
p1
p2
UGF
GM
p1
p2 z1
PM
Types of Compensation
• Miller - Use of a capacitor feeding back around a
high-gain, inverting stage.
– Miller capacitor only
– Miller capacitor with an unity-gain buffer to block the
forward path through the compensation capacitor.
Can eliminate the RHP zero.
– Miller with a nulling resistor. Similar to Miller but with
an added series resistance to gain control over the
RHP zero.
• Self compensating - Load capacitor
compensates the op amp (later).
• Feedforward - Bypassing a positive gain
amplifier resulting in phase lead. Gain can be
less than unity.
General Miller effect
v2
v1
i
v1
v2=
AVv1
i = (v1-v2)/Zf
=v1(1-AV)/Zf
= - v2(1-1/AV)/Zf
i=
v1/Z1
i
i=
-v2/Z2
Miller compensator capacitor CC
C1 and CM are parasitic capacitances
DC gain of first stage:
AV1 = -gm1/(gds2+gds4)=-2 gm1/(I5(l2+ l4))
DC gain of second stage:
AV2 = -gm6/(gds6+gds7)=- gm6/(I6(l6+ l7))
Total DC gain:
gm1gm6
AV =
(gds2+gds4)(gds6+gds7)
2gm1gm6
AV =
I5I6 (l2+ l4)(l6+ l7)
GBW = gm1/CC
Zf = 1/s(CC+Cgd6) ≈ 1/sCC
When considering p1 (low freq), can ignore
CL (including parasitics at vo):
Therefore, AV6 = -gm6/(gds6+gds7)
Z1eq = 1/sCC(1+ gm6/(gds6+gds7))
C1eq=CC(1+ gm6/(gds6+gds7))≈CCgm6/(gds6+gds7)
-p1 ≈ 1 ≈ (gds2+gds4)/(C1+C1eq)
≈ (gds2+gds4)/(C1+CCgm6/(gds6+gds7))
≈ (gds2+gds4)(gds6+gds7)/(CCgm6)
Note: 1 decreases with increasing CC
At frequencies much higher than 1, gds2
and gds4 can be viewed as open.
Total go at vo:
CC
gds6+gds7+gm6
CC+C1
Total C at vo:
C 1C C
C L+
CC+C1
M6
CC
vo
C1
-p2=2=
CCgm6+(C1+CC)(gds6+gds7)
CL(C1+CC)+CCC1
CL
M7
gds6+gds7
Note that when CC=0, 2 =
CL
As CC is increased, 2 increases also.
However, when CC is large, 2 does not
increase as much with CC. 2 has a upper
limit given by: g +g +g
gm6
m6
ds6
ds7
≈
CL+C1
CL+C1
When CC=C1, w2 ≈ (½gm6+gds6+gds7)/(CL+½C1)
Hence, once CC is large, its main effect is
to lower 1, and hence lower GBW.
Also note that, in contrast to single stage
amplifiers for which increasing CL improves
PM, for the two stage amplifier increasing
CL actually reduces 2 and reduces PM.
Hence, needs to design for max CL
There are two RHP zeros:
z1 due to CC and M6
z1 = gm6/(CC+Cgd6) ≈ gm6/CC
z2 due to Cgd2 and M2
z2 = gm2/Cgd2 >> z1
z1 significantly affects achievable GBW.
gm6/(CL+C1)
f (I6)
A0
1
2
z1 ≈ gm6/Cgd6
z2 ≈ gm2/Cgd2
-90
-180
No PM
gm6/(CL+C1)
f (I6)
A0
z1 ≈ gm6/Cgd6
z2 ≈ gm2/Cgd2
1
2
z1 ≈ gm6/Cc
-90
-180
No PM
gm6/(CL+C1)
f (I6)
A0
2
1
gm1/CC
-90
-180
PM
z1 ≈ gm6/CC
It is easy to see:
PM ≈ 90o – tan-1(UGF/2) – tan-1(UGF/z1)
To have sufficient PM, need UGF < 2
and UGF << z1
In such case, UGF ≈ GB
≈ gm1/CC = z1 * gm1/gm6.
GB < 2
GB << z1
PM requirement decides how much lower:
Hence, need:
PM ≈ 90o – tan-1(GB/2) – tan-1(GB/z1)
Possible design steps for max GB
•
•
For a given CL and Itot
Assume a current share ratio q, i.e.
–
•
Size W6, L6 to achieve max gm6/(CL+Cgs6)
which is > 2
–
•
this make z1 ≈ 10*GBW
Select CC to achieve required PM
–
•
•
C1  W6*L6, gm6  (W6/L6)0.5
Size W1, L1 so that gm1 ≈ 0.1gm6
–
•
I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2
by making gm1/CC < 0.5 2
Check slew rate: SR = I5/CC
Size M5, M7, M3/4 for current ratio, IMCR, etc
Comment
• If we run the same total current Itot through
a single stage common source amplifier
made of M6 and M7
– Single pole go/CL
– Gain gm6/go
– Single stage amp GB = gm6/CL >gm6/(CL+C1)
> 2 > gm1/CC = GB of two stage amp
• Two stage amp achieves higher gain but
speed is much slower!
• Can the single stage speed be recovered?
Other considerations
• Output slew rate: SR = I5/CC
• Output swing range: VSS+Vdssat7 to VDD –
Vdssat6
• Min ICM: VSS + Vdssat5 + VTN + Von1
• Max ICM: VDD - |VTP| - Von3 + VTN
• Mirror node approx. pole/zero cancellation
– Closed-loop pole stuck near by
– Can cause slow settling
When vin is short, the D1
node sees a capacitance CM
and a conductance of gm3
through the diode con.
So: p3 = -gm3/CM
When vin is float and vo=0.
gm4 generate a current in
id4=id2=id1. So the total
conductance at D1 is gm3 +
gm4.
So: z3 = -(gm3+gm4)/CM
=2*p3
If |p3| << GB, one closed-loop pole stuck nearby,
causing slow settling!
Eliminating RHP Zero at gm6/CC
icc = vg gm6
= CCdvCC/dt
vg= RZCCdvCC/dt
+vcc
CCdvCC/dt
(gm6RZ-1)CCdvCC/dt + gm6vcc=0
For the zero at M6 and CC, it becomes
z1 = gm6/[CC(1-gm6Rz)]
So, if Rz = 1/gm6, z1 → 
For such Rz, its effect on the p1 node can
be ignored so p1 remains as before.
Similarly, p2 does not change very much.
similar design approach.
Realization of Rz
vb
VDD
M8
M9
Another choice of Rz is to make z1 cancel
2:
z1=gm6/CC(1-gm6Rz) ≈ - gm6/(CL+C1)
CC+CL+C1
 Rz =
gm6CC
1 (1+ CL+C1 )
=
CC
gm6
Let ID8 = aID6, size M6 and M8 so that
VSG6 = VSG8
Then VSGz=VSG9
Assume Mz in triode
Rz = bz(VSGz – |VT| - VSDz)
≈ bz(VSGz – |VT|)
= bz(2ID8/b9)0.5
= bz(2aID6/b6)0.5(b6/b9)0.5
= bz/b6 *b6VON6 *(ab6/b9)0.5
= bz/b6 *1/gm6*(ab6/b9)0.5
Hence need: bz/b6 *(ab6/b9)0.5 =(CC+CL+C1)/CC
gm6/(CL+C1)
f (I6)
A0
-z1 ≈
2
1
gm1/CC
-90
-180
PM
• With the same CC as before
– Z1 cancels p2
– P3, z3, z2, not affected
– P1 not affected much
– Phase margin drop due to p2 and z1 nearly
removed
– Overall phase margin greatly improved
– Effects of other poles and zero become more
important
• Can we reduce CC and improve GB?
A0
gm6/CL
Operate not
on this
but on this
or this
z1 ≈ p2
1
-90
-180
2
z2 ≈ gm2/Cgd2
z4 ≈ gm6/Cgd6
Increasing GB by using smaller CC
• It is possible to reduce CC to increase GB if
z1/p2 pole zero cancellation is achieved
– Can extend to gm6/CL
– Or even a little bit higher
• But cannot push up too much higher
–
–
–
–
Other poles, zeros
Imprecise mirror pole/zero cancellation
P2/z1 cancellation
GB cannot be too high relative to these p/z
cancellation
• Z2, z4, and pz=-1/RZCC must be much higher
than GB
Possible design steps for max GB
•
•
For a given CL and Itot
Assume a current share ratio q, i.e.
–
•
–
•
•
•
–
•
Size W6, L6 to achieve max single stage GB1 =
gm6/(CL+Coutpara)
Make z4=gm6/Cgd6 > (10~50)GB1
Choose GB = aGB1,
Choose CC to make p2 ≈ GB/(10~20)
Size W1, L1 and adjust q so that gm1/CC ≈ GB
Make z2=gm2/Cgd2 > (10~20)GB
Size Mz so that z1 cancels p2
–
•
•
•
I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2
Make sure |pz| due to Mz and CC >> GB
Make sure PM at f=GB is sufficient
Size M3/4 so that gm3/CM is > GB/(10~20)
Check slew rate, and size other transistors for ICMR,
OSR, etc
Simple transistor circuits
• Can use any # of ideal current or voltage
sources, resisters, and switches
• Use one or two transistors
• Examine various ways to place the input
and output nodes
• Find optimal connections for
– high gain
– high bandwidth
– high or low output impedance
– low input referred noise
Single transistor configurations
• It’s a four terminal device
• Three choices of input node
• For each input choice, there are two
choices for the output node
• The other two terminals can be at VDD,
GND, virtual short (V source), virtual open
(I source), input, or output node
• Most connections are non-operative or
duplicates
– D and S symmetric; B not useful
2 valid input choice and 1 output choice
Connection of other terminals:
or
Resister
Capacitor
Gnd or virtual
Common source
To VDD
This is D
Source follower
N-channel common gate
p-channel common gate
Diode connections
Building realistic circuits from
simple connections
flip vertical 
N common source
Combine 
flip left-right 
N common source
Combine to form
differential pair 
flip upside down to get
current source load 
Vbb
Vbb
Combine to form
differential amp
Can also use self biasing
and convert to single
ended output 
Replace virtual gnd
by current source
two transistor connections
• Start with one T connections, and add a
second T
• Many possibilities
– many useless
– some obtainable by flip and combine from one
T connections
– some new two T connections
• Search for ones with special properties
– in terms of AV, BW, ro, ri, etc
First MOST is CS
D1 connects to D2:
(with appropriate n-p pairing)
-kvo
vo
vin
CS
Push pull
CS
CS with
negative gm at
output node
When Vx = gnd
T2 is not useful
VDD
When Vx = Vin, T2
and T1 are just one T
Vo
Vx
When Vx = -kVo
what do we get?
Vx=gnd, M2 is I source
VDD
Vo
Vx = vin, ?
Vx = ─ vin, ?
M1 M2
Vx = vo, capacitor
Vx
Vx = kvo, negative
gds feedback
VDD
VDD
M4
M3
vo
vin
k
M1
M2
M5
gm1vin+gds1vo+
gds3vo-kvogm3=0
-vo
k
AV=
-vin
gm1
gds1+gds3-kgm3
gds1+gds3
AV=  when k =
gm3
GBW=gm1/Co = GBW of simple CS
D1 connects to S2
VDD
just a single
NMOST
VDD
Cascode
VDD
any benefits?
VDD
-kVx
VDD
-kVo
Vo
Vx
Cascode
with positive
Vx feedback
Cascode
with positive
Vo feedback
VDD
VDD
Vin
Vo
Folded cascode
Vo
Effects on GBW?
VDD
VDD
Vx
-Vx
Vo
folded cascode with positive feedback
-kVo
Vo
VDD
Rb
Vbb
Vin
flip up-down
for source
Vyy
M2
M1
connecting D1 to S2
cascoding
CL
Vxx
Vbb
Vin
VDD
M4
M3
M2
M1
CL
VDD
flip left-right
to get this
differential
telescopic
cascoded
amplifier
VDD
Vyy
M7
M5
Vxx
M6
Vbb
M3
CL
M8
M1
M4
M2
Vin+
add M9 to change
gnd to virtual gnd
CL
VinM9
GBW=gm1/Co
VDD
VDD
Vyy
How to connect M7
G3 to –Vx, –kVx,
or – kVo
M5
Vo
M8
M6
M3
CL
M4
Vx
M1
M2
Vin+
Same GBW
Gain can be very high
CL
VinM9
VDD
VDD
Vyy
How to connect M7
G3 to –Vx, –kVx,
or – kVo
M5
Vo
M8
M6
M3
CL
M4
Vx
M1
M2
Vin+
Same GBW
Gain can be very high
CL
VinM9
flip up-down for
I sources
VDD
VDD
Vbb
M2
Vbb
Vin
Vin
M1
CL
connecting n-D to p-S
CL
VDDVDD
folded cascode amp
Same GBW
Vbb
Vin+
Vin-
CL
VDDVDD
How to connect for
positive feedback?
Vbb
Vin+
Vin-
CL
D1 connects to G2, two stages
VDD
VDD
two stage
CS amplifier
VDD
VDD
CS amplifier with a
source follower buffer
VDD
VDD
VDD
VDD
VDD
VDD
•Needs compensation and CM feedback
•Can gain be higher than single stage?
•Can GBW be improved vs single stage?
VDD
VDD
VDD
VDD
Vx
-Vx
Can you connect
without loading effect?
-vin
VDD
VDD
Vomin = Vin-min + Vdssat
or = VT + 3Vdssat
VDD
VDD
Biasing?
VDD
VDD
Vomin = 2Vdssat
VDD
VDD
VDD
VDD
But is the gain improved?
Is GBW improved?
VDD
VDD
V?
VDD
Vx
Vx
Same as above,
only T2 is pMOS
Connecting S1 to D2
makes ro really small
buffer or output stage
VDD
VDD
or
VDD
VDD
VDD
VDD
M1

connecting S1 to G2
VDD
Vx
Vx
VDD
VDD
VDD
VDD
Vx

Vx?
connecting S1 to S2
Vo
Vo
-Vin
connecting S1 to D2
V?
V?
?
?
e.g.

M1 is common gate:
D1 connects to G2
VDD
Vin
D1 connects to S2
Vin
PSRR
vout
Av 
vin
vout
Add 
vdd
vdd  vss  0
vin  vss  0
Ain
PSRR  
Add
vout
Ass 
vss
vin  vdd  0
Ain
PSRR  
Ass
Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout
 Vout(1+Av) = AddVdd
vdd 1  Av
Av


 PSRR 
vout
Add
Add
Good as long as Av >> 1, or f < GB
DC gain: ignore all caps and find
relationship between vdd and vout
at vout gm1 at Id1same at
Id2gm1/(gds2+gds4) at
G6vg6gm6/gds6 across DS6
vdd= gm1/(gds2+gds4)
*gm6/gds6
Vdd/vout =
gm6gm1/gds6(gds2+gds4)
For zeros, set vdd = 0,
vout float.
This is the unity gain buffer
configuration of the amp.
Hence, char roots are: -GB
and p2
For poles, make vout = 0, vdd float.
Three nodes: S3/S4/S6, G3/G4/D1: ignore
Write KCL at D2/D4/G6 node:
v(gds2+gds4+sCI+sCC)=vdd(gds4+gds1*1)
Current balance in M6:
gm6(v-vdd)=gds6vdd v=(1+gds6/gm6)vdd
gds6/gm6*(gds2+gds4)+(1+gds6/gm6)s(CI+sCC)=0
gds6/gm6*(gds2+gds4)=
-s(CI+sCC)
Pole at
- gds6(gds2+gds4)
/(gm6(CC+CI))
Similar computation for PSRR1. Get DC gain
2. Get zeros: they are
the same as in
PSRR+, and the
same as poles of
unity feedback Avd
3. Get dominant pole:
Practice this, and see if you get similar results
as in book
Two-Stage Cascode Architecture
• Why Cascode Op Amps?
– Control the frequency behavior
– Increase PSRR
– Simplifies design
• Where is the Cascode Technique Applied?
– First stage • Good noise performance
• Requires level translation to second stage
• Requires Miller compensation
– Second stage • Self compensating
• Reduces the efficiency of the Miller compensation
• Increases PSRR