Transcript Radeka_New_Directions_..._091506

Semiconductor Tracking Detectors
– New (Future?) Directions
Veljko Radeka, BNL
6th Int’l Hiroshima Symposium, Sept 15,2006
Acknowledgements: Gianluigi De Geronimo,
Paul O’Connor,
Zheng Li,
Pavel Rehak
1
-- “It is difficult to make predictions ….
… particularly about the future”.
(A well known 20th century philosopher)
-- “It is always wise to look ahead, but difficult to
look further than you can see”.
-- “The farther backward you can look, the
farther forward you are likely to see.”
-- “It is a mistake to look too far ahead. Only
one link of the chain of destiny can be handled
at a time.”
-- “I always avoid prophesying beforehand,
because it is a much better policy to prophesy
after the event has already taken place”.
Footnote: “It is a good thing for an uneducated
man to read books of quotations”
2
“History will be kind to us ...
… I intend to write it”
( W.C. ~1945)
3
Scope of the Semiconductor
“Tracking Detector” Field
Area of research:
• Particle physics
• Astro (particle) physics
- astronomical
observations (3501000 nm)
- x-ray
• Relativistic heavy ion
physics
• Synchrotron radiation
• Electron Microscopy
• Biology&Medical
Research
• Materials science
(various x-ray
techniques)
• Homeland security
Detector technology:
•Si-strips, p+p spray
Research Facility:
•Si-pixels
•LHC + upgrade
•Si-3d pixels
•RHIC + upgrades
•MAPS
•ILC
•APS on high rho Si
•Numerous light
sources (APS,
LCLS, NSLS, …
•Large telescopes
•Space instruments
•Hybrid PIN-CMOS
•SOI vertically
integrated – 3D
electronics
•CCDs & new
developments
•APDs & Geiger mode
In DOE BES
budget is bigger
than HEP!
•Materials: Si, Ge, CZT, SiC,
Diamond
•STJs, STE, bolometers, ..
Monolithic Electronics
4
Electron – (hole, ion) creation energy
wi [eV]
Application:
5
Outline
1. Main stream (established!) directions in developments
for forthcoming applications (strips and hybrid pixels for
LHC, RHIC, …)
2. Examples of some interesting special applications
3. Impact of developments in microelectronics
4. What we would like to see developed in pixel
detectors (for light, x-rays and charged particles, ILC,
astrophysics) → Merging of detectors and
electronics
6
Outline
1. Main stream (established!) directions in developments
for forthcoming applications (strips and hybrid pixels for
LHC, RHIC, …)
2. Examples of some interesting special applications
3. Impact of developments in microelectronics
4. What we would like to see developed in pixel
detectors (for light, x-rays and charged particles, ILC,
astrophysics) → Merging of detectors and
electronics
7
1. Developments for LHC and RHIC Ugrades
• Radiation hardness: - Oxygen and p-spray are here to stay
Medium resistvity p material, short
strips, thinner substrate, lower noise
electronics; 3D electrodes in the vertex;
- Silicon will remain material of choice.
Materials “damaged to begin with” (GaAs)
will remain “materials of the future”.
• Preferred readout: - single-sided. ac-coupling needed for
detector testing.
dc-coupling: feedback methods developed to
absorb leakage currents dc-coupling (see: G.
De Geronimo, )
• Vertex in RHIC:
MAPS
8
Outline
1. Main stream (established!) directions in developments
for forthcoming applications (strips and hybrid pixels for
LHC, RHIC, …)
2. Examples of some interesting special applications
3. Impact of developments in microelectronics
4. What we would like to see developed in pixel
detectors (for light, x-rays and charged particles, ILC,
astrophysics) → Merging of detectors and
electronics
9
Zhong He, et al.: 3-Dimensional Position Sensing in CZT….
Trapping of electrons and material non-uniformity in Z
 Depth sensing (EE, z)
Cathode
h+
e-
C
Pixellated
anodes
A1

Single-interaction events:
C/A = depth of interaction
t1  z1


A1
Z1
Z2
A2
Multiple-interaction events:
Drift-times  individual Zs
A1
C
Triggers
C
h+ e-
A2
t2  z2
Time
10
Zhong He, et al.: 3-Dimensional Position Sensing in CZT….
 Recognize the type of radiation for background reduction
(Internal induced +, - decays, activation -, charged particles)
A TPC approach:
Observation of muon tracks
Measured
Energy deposition
Detector: 1.51.51 cm3 CdZnTe
11
Si-pixel detectors in electron microscopy (see also the talk
by P. Denes)
Multiple scattering of 200keV electrons in 200 mm of silicon
Rehak et al.
12
Multiple scattering of 200 keV electrons in 30 mm of silicon
Thin detector needed!
13
Multiple scattering of 200 keV electron in 30 mm Si & 500
mm Be
14
Avalanche Photodiodes for LSO
used in PET (BNL project)
Hamamatsu S8550
4x8 array
1.6 x 1.6 mm2
active pixel area
CT~ 10 pF
Typical G ~ 50
Npe ~ 1200
~ 60K signal electrons
Expected noise in final
ASIC ~ 500-600 e’s
15
Outline
1. Main stream (established!) directions in developments
for forthcoming applications (strips and hybrid pixels for
LHC, RHIC, …)
2. Examples of some interesting special applications
3. Impact of developments in microelectronics
4. What we would like to see developed in pixel
detectors (for light, x-rays and charged particles, ILC,
astrophysics) → Merging of detectors and
electronics
16
The “Roadmap” (1)
The “Roadmap” (2)
Detector Physicist: “Electronics is Cheap!”
Cost per transistor:
But …
… supply and threshold voltages have not
followed the scaling …
Proc. IEEE
Threshold mismatch due to
discrete dopant
distribution
3D p-MOSFET simulation with
stochastically placed dopants
D.J. Frank, IBM J. Res. Dev. 46, 235-244, Mar./May 2002
VT
Dopant atoms per MOSFET
1000
500
0
0.25
0.18
0.15
0.13
Lmin, mm
0.1
0.07
21
fT vs power
1011
65nm
Bandwidth for
low power
analog is not as
high as the
advanced
technology
might indicate
fT, Hz
1010
109
130m
108
107
250nm
10-6
10-4
P, W
10-2
Gain gm/gds degraded in ultra-scaled
devices:
• Speed/intrinsic gain
tradeoff
• failure to adhere
to classical
constant-E scaling
20
fT
200
gm/gds
15
150
10
100
gm/gds
fT, GHz
– fT ~ 1/LG for min-LG
devices
– Output conductance
gds sensitive to
geometry and bias
– Gain gm/gds
degraded in ultrascaled devices:
250
5
50
0
0
250
180
130
90
65
Technology Node, nm
23
Analog design becomes more difficult with
scaling of CMOS
• The low supply voltage headroom in scaled CMOS
processes imposes limits on analog circuit topologies.
The increasing ratio of VTH/VDD rules out the use of
many classical analog design topologies.
• The cascode connection, useful in providing high gain
loads and current sources, becomes dificult once VDD
falls below ~1.2V.
• CMOS transmission gates, commonly found in
sample/hold and switched capacitor circuits, perform
poorly in scaled processes as the control gate voltage is
limited and self-discharge rates increase.
• Source followers limit the available signal swing and
have to be avoided in output stages and other largesignal circuit blocks.
P. O’Connor, SNIC 2006
Gate tunneling current
•
Gate current expected to increase
100 – 200 x per generation below
0.18 mm
•
Jox ~ 100 A/cm2 projected for Lmin =
0.1 mm generation with nitrided SiO2
•
Considered tolerable for digital
circuits (total gate area per chip ~
0.1 cm2)
•
Typical input FET would have I G ~ 1
nA at 1 µsec for 130 nm;
ENCp , increasing exponentially with
scaling
SiO2 gate leakage current (Lo et al., Electron Dev.
Letters 1997)
25
Active and Passive Power Density vs Gate Length
IBM J. Res. Dev.
What at the end of the Roadmap?
Stages of nanoscale devices future development:
http://www.research.ibm.com/journal/rd/, Sept. 2006
Performance
enhancement
by 1d and 2d
carrier
confinement,
Carbon
nanotube
(CNT) FETs
-----------------Distant future:
new devices
such as spin
transistors –
different
architecture
IBM J. Res. Dev.
Single electron and single molecule transistors
(1) single electron transistors (first
introduced By K. Likharev in 1985)
Tunnel junctions
Quantum dot
Coulomb blockade:
1 e on 1 aF ~ 160 mV
~1 aF
(kTC)1/2~ 0.4 e rms at 300K
Electrometer noise:
~ 10-5 e rms/Hz1/2
Single Molecule (Electromechanical) Transistor:
(studies of carbon nanotubes)
C. Joachim, Proc.
IEEE,86(1998)184
Bell
Labs
Dec.
1947
The use of single electron transistors in
particle and photon detectors is
somewhat beyond the horizon….
However, if the detectors ever get to
nanoscale voxels, and less than ~ 10
atofarads, then…
(we are now at a few femtofarads)
Toward merging of detectors and
electronics …
Goal: Detector thickness optimized to application
(from ~30μ to ~2mm), with all appropriate
readout functions, different in each case
• Developments in CCDs for astronomy, x-ray
and particle physics
• PIN-CMOS bump bonded hybrids
• Single transistors on high resistivity silicon
• MAPS for ILC
• Bonding of low resistivity silicon (CMOS) to
high resistivity silicon detector; single layer or
multilayer (3D) electronics
33
CCDs - Partial vs Full Depletion
•
Conventional CCDs 15-20 µm
thick on 20-100 ohmcm silicon
cannot be fully depleted with
15-20 volts.
PSF (rms) ~ thickness of
undepleted region (≥~6-7 µm)
•
Full depletion essential for
minimal charge spreading,
PSF (rms) < ~ 4 µm
•
Methods to ensure full
depletion:
– High-resistivity substrate
>5 kohm cm
– Bias on p+ (n+) backsurface (30-50 volts on 100
µm)
Illustration from:
Barry Burke
Fully depleted thick CCDs
pioneered by S. Holland,
LBNL
34
Critical technology issues for thick overdepleted sensors for
astronomy:
1. 3d-layout, doping&biasing of p+ and
n+ regions, guard ring design to allow
independent biasing of the (back side)
sensor window.
2. Conductive (ohmic) window to allow independent
biasing, and not absorb near-UV.
 E  qe N x
E ~ 3kV/cm
A 3-phase CCD shown
schematically along the charge
transfer direction. A p-channel (nsubstrate) device is indicated. The
readout node capacitance is
typically 15 to 30fF, corresponding
to a conversion gain of between
~10 and ~5 microvolts/electron
respectively.
CCD view across the buried
channel and the channel stops. The
potentials among the channel, the
channel stops and the window must
be arranged so that the conduction
path between the window and the
channel stops is pinched-off , i.e.,
that the field lines from the window
reach the buried channel and not
the channel stops
V. Radeka, SNIC 2006
p
N~1012/cm-2
~ 5-10 kohmcm
5-10 nm
p++
N~1019/cm3
An illustration of the termination of electric
field at the window of an overdepleted
sensor. A highly doped layer at the
window is required to bring the electric
field to zero before it can reach the
surface, and to leave a thin (a few nm)
35
conductive layer at the surface.
Multi-port 4K x 4K = 16M CCD
Column Parallel Readout
Blooming column
length 2000 pixels
2 contiguous imaging
areas 2kx4k separated
by a blooming stop less
than 1-2 pixel rows wide
Readout segment boundary (no discontinuity)
Dog-leg output: (R. Bredthauer, STA)
500x
2000
36
Readout Noise in CCDs
Lincoln Labs
Sense-node capacitance~5 fF
(20 µV/e-)
10e
15fF
Source Follower transistor:
By CCD process:
MOS(P):
Channel length L:
~4-6 μm
Channel width W:
~45 μm
C
~0.4-0.5 μm M
M
~10 μm
Power:
5-10 mW
<100 μW
Results From: Burke, Jorden, Vu, SDW Taormina 2005
1 MHz
For equal
noise!
Short Column 2-phase CCD (SCCCD)
Bunch
6
5
4
3
12
M. Breidenbach,
Presentation at this
Symposium
Time Amplitude
15 8
18 5
CCD Clock
16
3
5
8
7
14
18
17
20
4
16
9
13
12
11
15
• Utilizes CCD correlation of position with bunch twice to “solve” for
position and bunch time.
• Clock CCD at ~10 MHz
• Use LHC style bump bonding for connections.
• Occupancy of a short column/column read time ~0.5 (inner layer)
• Once the bunch is identified, then ~no ambiguity for position.
38
PIN-CMOS
•Independent optimization of the PIN
and CMOS design and processing
•Electronic shutter by reset
transistors
•Blooming control
•Large dynamic range by readout “up
the ramp”; addressable guider
readout
•Lower power dissipation, low voltage
for CMOS
•Fixed pattern noise
•pixel-to-pixel (stable) gain
differences due to amplifier per
pixel
•capacitive (deterministic) crosstalk
to adjacent pixels
•CDS over longer time intervals
J. Beletic. Et al.:
Indium Bump Bonds (samples, ATLAS, CMS)
H. Krueger, NIM A 551(2005)1
40
Indium Bump Bonding
Bond yield by RVS and RSC
>0.999
Indium interconnect array on 8 um centers
compared to a human hair.
From: K.T. Veeder et al., “Enabling Technologies
for Large Hybrid Focal Plane Arrays with Small
Pixels”, Raytheon Vision Systems
The DEPFET Principle (from N. Wermes)
Potential distribution:
source
top gate
n+
p+
p-channel
bulk
p+
n+
--n-- +
-+ -
internal gate
-+
totally depleted
n--substrate
-
sourcetop gate drain
symmetry axis
1 mm
potential minimum
for electrons
internal Gate
50 µm
- 300 mm
p+
rear contact
p+
potential via axis
top-gate / rear contact
n+
V
+15
0
0 V
clear
V
V
bulk
n+
n+
p+
p
n
-----internal gate
CLEAR complete ?
nlow noise (no N, no
kT/C )
fast pedestal subtraction
•
•
p+
rear contact
•
50 µm
+
drain
[TeSCA-Simulation]
p-channel JFET or MOSFET integrated on
high-ohmic n-substrate, sidewards-depleted
(as in drift det., Gatti, Rehak, 1983).
electrons are collected in an internal gate
close to the surface
the device can be switched on/off by an
external (top) gate
J. Kemmer und G. Lutz;, NIM A253 (1987) 365
“JFET switch on high rho (~10 kohm cm) Si”:
X-ray passive matrix pixel
P. Rehak, et al.
43
MOSFET on high rho Si (IBM process)
●
Circularly symmetric MOSFET
replaces similar JFET in the
previous design


Thin gate (5nm) oxide is
rad-hard
Circular symmetry is
automatically 'enclosed
gate' design
S
CVD / SOG
CVD / SOG
G
BPSG
G
BPSG
FOX
BPSG
BPSG
FOX
3 µm
S
S
500 µm
7 µm
S
Row
3 µm
D
G
S
D
Passivation
7 µm
●
n-type
●
Weak p
●
n+ implant
●
Metal 1
●
p+ implant
●
Metal 2
●
SiO2
●
Polysilicon
S
Column
Collaboration: P. Siddons 44
et al.
Monolithic Active Pixel Sensor (MAPS)
• Fabricated on standard CMOS
silicon wafer
• Charge produced in p- epitaxial
layer diffuses to active junction
•Thin active layer (2 – 10 mm), low
signal
• Diffusive charge collection  long
collection times, large lateral spread
• Charge removed by reset transistor
• In-pixel electronics limited to one
transistor type
• Chip size limited
VDD
RE_SEL
ROW_SEL
COLUMN LINE
metal
n+
nwell
pwell
photo diode
poly
diffusion isochron
Deptuch, et al;
Kleinfelder, et al.,;
…………………….
……………………….
45
MAPS for ILC?
•
Marty B. (this Symposium):
“Bunch identification (probably) requires all pixels to be continuously sensitive
throughout the train.
– So ~1x109 front end amplifiers must be on for 1 ms.
– Unlikely that the current in each amplifier will be less than 1 μAmp
– So vertex detector needs ~1000 ampere supply”
Gianluigi De Geronimo, BNL:
Amplifier before the
comparator needed due to
small signal from the thin epi
layer:
Gain: 8
VDD= 1.4 V
I= 200 nA
in <100ns
ENC~ 40 e rms
Including the comparator, the
current is expected to be ¼ to
1/3 of Marty’s assumption.
Trends:
• High performance (“scientific”) CCDs ~75-200 μm thick
for astronomy (more for x-rays) –
-being developed by several manufacturers.
• Column parallel conventional CCD readout (transistor on the
chip) will be limited to a small number of segments (power
dissipation, number of connections).
• Silicon PIN CMOS bump bonded hybrids remain to be
proven and accepted in astronomy. If so, will prevail for
short integration/readout times. CCDs will still be best for
long integration times.
• CCD-CMOS hybrids need to be explored for high
performance imaging in astronomy (they are being actively
developed for other fields). No extreme CCD flatness and
thin window requirements for particle physics.
Bonding of low resistivity silicon (CMOS) to
high resistivity silicon detector; single layer or
multilayer (3D) electronics
• Information:
-- R. Jarema, Perugia 2006 FEE
-- A. Klumpp, et al., - “ –
-- R. Lipton, this Symposium
First significant goal: bonding of 1 layer of fully
functional CMOS with high rho Si:
-- 50 microns would improve the MAPS.
-- 0.5 to 2 mm will benefit various x-ray detectors.
… then 3D with optimized analog and digital functions