Transcript Transistors and Layout 1

Topics
Basic fabrication steps
 Transistor structures
 Basic transistor behavior

Modern VLSI Design 2e: Chapter 2
Copyright  1998 Prentice Hall PTR
Fabrication services

Educational services:
–
–
–
–

U.S.: MOSIS
EC: EuroPractice
Taiwan: CIC
Japan: VDEC
Foundry = fabrication line for hire.
Modern VLSI Design 2e: Chapter 2
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-based design
 is the size of a minimum feature.
 Specifying  particularizes the scalable
rules.
 Parasitics are generally not specified in 
units.
 In our 0.5 micron process, =0.25 microns.

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Fabrication processes

IC built on silicon substrate:
–
–
some structures diffused into substrate;
other structures built on top of substrate.
Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
 Wires made of polycrystalline silicon
(poly), multiple layers of aluminum (metal).
 Silicon dioxide (SiO2) is insulator.

Modern VLSI Design 2e: Chapter 2
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Photolithography
Mask patterns are put on wafer using photosensitive material:
Modern VLSI Design 2e: Chapter 2
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Process steps
First place tubs to provide properly-doped
substrate for n-type, p-type transistors:
p-tub
p-tub
substrate
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Process steps, cont
Pattern polysilicon before diffusion regions:
poly
p-tub
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gate oxide
poly
p-tub
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Process steps, cont
Add diffusions, performing self-masking:
poly
n+
p-tub
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poly
n+
p+
p-tub
p+
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Process steps, cont
Start adding metal layers:
metal 1
metal 1
vias
poly
n+
p-tub
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n+
poly
p+
p-tub
p+
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Transistor structure
n-type transistor:
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0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
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Transistor layout
n-type (tubs may vary):
L
w
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Drain current characteristics
Modern VLSI Design 2e: Chapter 2
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0.5 m transconductances
From a 0.5 micron process:
 n-type:
–
–

kn?= 73 A/V2
Vtn = 0.7 V
p-type:
–
–
kp?= 21 A/V2
Vtp = -0.8 V
Modern VLSI Design 2e: Chapter 2
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Current through a transistor
Use 0.5 m parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.
 Vgs = 2V:
Id 0.5k?W/L)(Vgs-Vt)2= 93 A

Vgs = 5V:
Id = 1 mA
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Basic transistor parasitics
Gate to substrate, also gate to source/drain.
 Source/drain capacitance, resistance.

Modern VLSI Design 2e: Chapter 2
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Basic transistor parasitics, cont
Gate capacitance Cg. Determined by active
area.
 Source/drain overlap capacitances Cgs, Cgd.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.

–

Cgs = Col W
Gate/bulk overlap capacitance.
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Latch-up
CMOS ICs have parastic silicon-controlled
rectifiers (SCRs).
 When powered up, SCRs can turn on,
creating low-resistance path from power to
ground. Current can destroy chip.
 Early CMOS problem. Can be solved with
proper circuit/layout structures.

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Parasitic SCR
circuit
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Parasitic SCR structure
I-V behavior
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Solution to latch-up
Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.
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Tub tie layout
p+
metal (VDD)
p-tub
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Body effect
Reorganize threshold voltage equation:
Vt = Vt0 + Vt
 Threshold voltage is a function of
source/substrate voltage Vsb.
 Body effect  is the coefficienct for the Vsb
dependence factor.

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The modern MOSFET
Features of deep submicron MOSFETs:
– epitaxial layer for heavily-doped channel;
– reduced area source/drain contacts for lower
capacitance;
– lightly-doped drains to reduce hot electron
effects;
– silicided poly, diffusion to reduce resistance.
Modern VLSI Design 2e: Chapter 2
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Circuit simulation
Circuit simulators like Spice numerically
solve device models and Kirchoff laws to
determine time-domain circuit behavior.
 Numerical solution allows more
sophisticated models, non-functional (tabledriven) models, etc.

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Spice MOSFET models
Level 1: basic transistor equations of
Section 2.2; not very accurate.
 Level 2: more accurate model (effective
channel length, etc.).
 Level 3: empirical model.
 Level 4 (BSIM): efficient empirical model.
 New models: level 28 (BSIM2), level 47
(BSIM3).

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Some (by no means all) Spice
model parameters
L, W: transistor length width.
 KP: transconductance.
 GAMMA: body bias factor.
 AS, AD: source/drain areas.
 CJSW: zero-bias sidewall capacitance.
 CGBO: zero-bias gate/bulk overlap
capacitance.

Modern VLSI Design 2e: Chapter 2
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Topics
Wire and via structures
 Wire parasitics
 Transistor parasitics

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Wires and vias
metal 3
metal 2
vias
metal 1
poly
n+
p-tub
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poly
n+
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Metal migration
Current-carrying capacity of metal wire
depends on cross-section. Height is fixed,
so width determines current limit.
 Metal migration: when current is too high,
electron flow pushes around metal grains.
Higher resistance increases metal migration,
leading to destruction of wire.

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Metal migration problems and
solutions
Marginal wires will fail after a small
operating period : infant mortality.
 Normal wires must be sized to accomodate
maximum current flow:

Imax = 1.5 mA/m of metal width.

Mainly applies to VDD/VSS lines.
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Diffusion wire capacitance

Capacitances formed by p-n junctions:
sidewall
capacitances
depletion region
n+ (ND)
substrate (NA)
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bottomwall
capacitance
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Poly/metal wire capacitance

Two components:
– parallel plate;
– fringe.
fringe
plate
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Metal coupling capacitances

Can couple to adjacent wires on same layer,
wires on above/below layers:
metal 2
metal 1
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metal 1
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Example: parasitic capacitance
measurement
n-diffusion: bottomwall=2 fF, sidewall=2 fF.
 metal: plate=0.15 fF, fringe=0.72 fF.

1.5 m
3 m
0.75 m
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1 m 2.5 m
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Wire resistance

Resistance of any size square is constant:
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Transistor gate parasitics

Gate-source/drain overlap capacitance:
gate
source
drain
overlap
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Transistor source/drain parasitics
Source/drain have significant capacitance,
resistance.
 Measured same way as for wires.
 Source/drain R, C may be included in Spice
model rather than as separate parasitics.

Modern VLSI Design 2e: Chapter 2
Copyright  1998 Prentice Hall PTR