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MASTERS OF MEMORY’S: Z-RAM
KUMARI INDU
ROLL NO: 70
B.E COMPUTER
B.V.U.C.O.E.
IEEE STUDENT MEMBER
Overview
Introduction
Memory types
Silicon-On-Insulator (SOI)
Z-RAM
Floating body effect
Advantages
Comparison
Future scalability
Z-RAM generation 2
Conclusion
Bibliography
Introduction
Today’s state of art microprocessor should not be
thought of as logic chips with embedded memory
rather should be called as memory chips with
embedded logic.
As processors go faster main memory goes
slower.
With each succeeding generation, main memory
access takes longer in terms of processor cycles.
Challenges
Shrinking die size
Reducing cost
Memory vs. die size
Present on chip
memory takes 50
percent of the
available area of any
respectable
microprocessor.
83 percent of the
area of high-end
processors made in
2008 and 90 percent
by 2010.
Semiconductor Industry Association (SIA),
and the International Technology Roadmap
for Semiconductors (ITRS 2000).
Available memory types
SRAM
DRAM
eDRAM
A six-transistor CMOS SRAM cell
Simple 4 by 4 array
SRAM VS. DRAM
6T per bitcell.
No refreshing.
Lower density.
Bit lines are actively
driven high and low thus
increase speed.
Accept all address bits
at a time.
1T/1C per bit cell
Refreshing required
Very high density
The bit line connected to
capacitors causes the
bitline to swing upwards or
downwards.
Address multiplexed in two
halves(higher followed by
lower)
Though slower than SRAM, DRAM consumes about onefifth as much power and is about four times as dense
Silicon-on-insulator (soi)
A very thin layer of insulating silicon dioxide buried a
few hundred nanometers below the surface.
Layer of insulation cuts the transistors off from the
vast bulk of the wafer-which limits the amount of
charge the transistor must move in order to switch on
or off.
speed up the circuits by 30 percent when switching.
Insulation in SOI wafers blocks a major power that
transistors draw by 30 percent when they are
switching and 50 percent to 90 percent when they are
not.
SOI (contd…)
200 millimeter SOI wafer sells for about $275.
A plain silicon wafer of the same size costs $65.
All things being equal SOI chip will cost almost 9
percent more than the bulk-silicon chip.
SOI’s insulating layer is a key to storing the bit in
Z-RAM.
Z-RAM would let designers shrink a chip to 72
square millimeters from 120 square millimeters.
SOI looks like a bargain.
SOI (contd…)
SOI die-cost reduction from bulk CMOS
Cell layout of SOI standard cells
library for 90nm process
SOI VS. BULK
SOI
Performance
10-30% better
Power
30% Lower active power;50%-90% lower
Standby power
Soft Error Immunity
Typically 5x better
Cost
Dies cost cheaper w/Z-RAM
Yield
AMD publicly claims SOI same yield as
bulk
Design Infrastructure
Growing
BULK
Big problem in newer nodes
Processed wafer 8%-15% cheaper
More investment today
Z-RAM
True capacitor-less, single
transistor DRAM.
Floating body effect SOI.
2X memory density of existing
eDRAM technology and 5X that
of SRAM.
Requires no special materials or
extra mask/process steps.
Lower cost and high
performance.
Reduced standby power
Highly Scalable
Configuration
eDRAM requires a deep
trench capacitor
structure with a
transistor for each
cell.
Stacked structure
of DRAM.
ZRAM requires
only one transistor
per bit cell
Floating body effect
Insulation layer in an
SOI wafer
electrically separates
the body of the
transistors from the
rest of the silicon,
letting its voltage
vary, or “float’.
NMOS Floating body
charging to write:
a) “1”
b) “0”.
Reading current from
ZRAM bit-cell.
Difference between 1 and 0 was just 3 to
15microamps per micrometer of channel width.
Advantages
increasing memory density with
reduced cost
Less power consumption
Demonstrated ~ 30 percent less power
consumption than eDRAM.
Greater speed
Fulfills wide range of product
requirements through different
architectures.
Asynchronous
Synchronous
Pipelined
Early write
Late write
Ultra-high density
reduces wire lengths
Reduced word line, bit-cell and bit line
capacitance
40% less capacitance than eDRAM
Promises continued improvements as
geometries shrink
comparison
Feature
DRAM
SRAM
Flash
MRAM
PCM
ZRAM
Cell size
8F2
100F2
4F2
20-40F2
6-8F2
4F2
Cell complexity
1T/1C
6T
1T
1T/1MTJ
1T/1R
1T
Volatility
Volatile
Volatile
Non Volatile
Non Volatile
Non Volatile
Volatile
Speed
Fast
Ultra fast
Very Slow
Fast
Fast
Fast
Wr./er./read time
ns/ns/ns
ns/ns/ns
µs/ms/ns
ns/ns/ns
ns/ns/ns
ns/ns/ns
Read
Destr.
Destr.
Non Destr.
Non Destr.
Non Destr.
Non Destr.
Refresh
yes
no
no
no
no
yes
New materials
Ba,Sr
None
None
Co,Fe,Ni,Mn,
Pd,Al2O3
Ge,Sb,Te
None
Scalability limits
Capacitor
Bitstable flip
flop
Tunneling
on Fl.
Gate
Spin Polar.
Phase change
Charge in FB
Process Maturity
Volume
prod.
Volume
prod.
Volume
prod.
Test chips
Single cells
Test chips
WAFER COST COMPARISION
DIE COST COMPARISION
Technology roadmap
Z-ram generation 2
Reduced power consumption
Greater difference between “1” & “0” current.
Standard manufacturing processes
Stores significantly more charge in the memory
bitcell
Much faster data read and write times greater
than 1GHz operation (when pipelined)
Enormous flexibility
Technology can be ‘tuned’ for a very wide range of
speed/power operating points, from ultra-low power
to very high performance
APPLICATIONS
Z-RAM FinFET bit-cell
fabricated for test purpose
conclusion
ZRAM technology based on SOI
processing will address market need for
highly dense memory that will scale to
the process nodes that will be in use for
at least 10 years – with no cost
penalty, no extra processing steps and
using no exotic materials or physics.
Bibliography
“Soft Error Performance of Z-RAM Floating Body Memory” by Fisch, D.;
Beffa, R.; Bassin, C. at International SOI Conference, 2006 IEEE Oct. 2006
Page(s):111 – 112.
“Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on
FinFET and tri-gate devices” by
Bassin, C.; Fazan, P.; Xiong, W.; Cleavelin, C.R.; Schulz, T.; Schruefer, K.;
Gostkowski, M.; Patruno, P.; Maleville, C.; Nagoga, M.; Okhonin, S. at SOI
Conference, 2005. Proceedings. 2005 IEEE International 3-6 Oct. 2005
Page(s):203 - 204
“RealView Hardware Platforms Product Selector” by Javier Orensanz ,July
2006
“Innovative Silicon’s Tiny DRAM Cells Alter the Memory Equation” By Tom R.
Halfhill , 10/25/05-03
Z-RAM Zero capacitor Embedded Memory Technology addresses dual
requirements of die size and scalability by Dr. Pierre Fazan,CTO ISi.
Electronics design magazine.
www.spectrum.ieee.org
www.innovativesilicon.com
www.zram.com
www.wikipedia.com
Thank you