Transcript Alice1 pixel readout chip

Pixel readout electronics development for
ALICE PIXEL VERTEX and LHCb RICH
W. Snoeys, M. Campbell, E. Cantatore, V. Cencelli*,
R. Dinapoli**, E. Heijne, P. Jarron, P. Lamanna**,
A. Marchioro, D. Minervini**, V. Quiquempoix,
D. San Segundo Bello***, B. van Koningsveld, K.
Wyllie
EP Division - CERN, Geneva
*Rome III university **INFN and Politecnico Bari
***Nikhef
Outline

Previous full readout chips



Two testchips







0.5 mm CMOS
0.25 mm CMOS
New chip for ALICE pixel and LHCb RICH


Omega2
Omega3/LHC1
Chip description
Design for radiation tolerance
Design for testability
Design for uniformity
Special issues
Conclusions
Omega2
Title:
(o2chip.pic t\023)
Creator:
(NIH Image 1.55: LaserWriter 8 8.4.2)
Preview :
This EPS picture w as not saved
w ith a preview included in it.
Comment:
This EPS picture w ill print to a
PostScript printer, but not to
other ty pes of printers .
Data
in
Delay
line
Cfb
Input
Threshold
control
current

-A
Coinc.
unit
D
Q
Ctest









Binary position information
Delay control
Strobe
Test Input
Reset
current
(only test row)
Pixel 75x500 mm2, 64 rows by 16 columns
Leakage current sensing cell at the bottom of each column
Internal delay per pixel (current deprived invertors), dead for twice the
trigger delay
Shift register readout after level 1 trigger
Limited testability : only one test row at the top
Two metal layers only : no shielding between electronics and detector
~ 80 transistors/pixel (Self Aligned Contact 3 mm technology)
Dies at < 50krad
Data
out
Omega3/LHC1




A




Discriminat
or

Pixel 50x500 mm2, 128 rows
by 16 columns
Internal delay per pixel
(current deprived invertors),
front end reset after small
fraction of the trigger delay
Shift register readout after
level 1 trigger
All pixels can be tested
electrically
Third metal shield
~ 380 transistors/pixel (Self
Aligned Contact 1 mm
technology
Dies at < 50krad
Discriminator (see left) tradeoff between threshold
uniformity and speed
Preamplifier feedback
Omega3 testability gave a wealth of information
Top-down threshold
variation due to
resistive drop
fixed in correction
run
3 bit delay adjust on half plane (~ 50 000
channels)
Title:
delplane7_0.eps
Creator:
HIGZ Version 1.23/07
Prev iew :
This EPS picture w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS picture w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.
Title:
delplane7_8.eps
Creator:
HIGZ Version 1.23/07
Prev iew :
This EPS picture w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS picture w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.
Before
After
Omega2 and Omega3 worked well
(CERN RD-19, WA97 and NA57)
Title:
(bump3dbw .eps)
Creator:
(ImageMagic k)
Preview :
This EPS picture w as not saved
w ith a preview included in it.
Comment:
This EPS picture w ill print to a
PostScript printer, but not to
other ty pes of printers .
LHC1 : 2000 CMOS
readout channels
Pixel Ladders
(6 chips)
Title:
(sourc e10bw .eps)
Creator:
(ImageMagic k)
Preview :
This EPS picture w as not saved
w ith a preview included in it.
Comment:
This EPS picture w ill print to a
PostScript printer, but not to
other ty pes of printers .
Half plane ~ 50 000 sensing
Title:
(153trac kbw .eps)
Creator:
(ImageMagick)
Prev iew :
This EPS picture w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS picture w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.
WA97 NA57 Experiment
1.2 M channels
Two test chips in
commercial submicron CMOS
Title:
(pix chip0.5.eps )
Creat or:
(ImageMagick)
Prev iew :
This EPS pict ure w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS pict ure w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.
2 columns of 64
pixels + 1 test
pixel with analog
outputs
 radiation tolerant
layout
 2 by 5 mm2
 full mixed mode
circuit
LHC2TEST/ALICE1TEST

0.5 mm CMOS
25000 transistors
Title:
(pixelc hip. eps)
Creator:
(ImageMagic k)
Preview :
This EPS picture w as not saved
w ith a preview included in it.
Comment:
This EPS picture w ill print to a
Post Script print er, but not to
ot her ty pes of printers .
ALICE2TEST
0.25 mm CMOS
50000 transistors
Changes in front end
Preamplifie
r
Shape
r
Vref
In
Cfb
IN



OUT
DC level of input and
output no longer coupled
Leakage current
compensation
ref : F. Krummenacher,
Nucl. Instr. and Meth., Vol.
A305 (1991) 527-532
Vbias
Threshold
setting

Iout to current
comparator
Change in discriminator for
speed, went to current
comparator
1200
1000
800
600
400
200
0
70
50
30
10
Input (mV) ( thresh. ~ 2100 el.)
Ileak = 1.4 nA, noise ~ 180 e rms
Ileak = 16 nA, noise ~ 210 e rms
Ileak = 100 nA, noise ~ 330 e rms
Leakage current compensation
works (for both signs of
leakage)
Added delay (ns)
Counts (pro mille)
0.5 mm test chip
60
40
20
0
0
5000
10000
15000
20000
Input charge (electrons, uncalib.)
threshold = 1650 el.
threshold = 2000 el.
threshold = 6400 el.
Timewalk LHC
compatible
electrons
0.5 mm test chip : evolution of
Threshold and Threshold Variation
with Xray Dose
3000
2500
2000
1500
1000
500
0
0
Threshold
500
1000
Dose (kRad)
Threshold variation (rms)
Supply currents virtually unaffected during the irradiation !
Circuit dies around 1 Mrad because of transistor Vt-shifts
which are still non-neglegible in 0.5 mm
Confirmed for electrons, and for (cfr. F. Meddi et al.) gamma-rays
and protons
0.5 mm test chip : conclusions




Mismatch for edgeless
transistors
cfr. G. Anelli et al.
Threshold dispersion too large
: edgeless transistor show
much larger mismatch (see
left)
=> need other front end
topology
Motivations to go deeper
submicron :
 Need more density
 Will get even higher
radiation tolerance
Need for further modeling of
edgeless transistors
Input structure
160 mm
Test FF
0.25 mm testchip
Front end
125 mm
Delay Mask FF + R/O
60 mm
125 mm
80
420 mm
Title:
(p2cells. eps)
Creator:
(ImageMagic k)
Preview :
This EPS picture w as not saved
w ith a preview included in it.
Comment:
This EPS picture w ill print to a
Post Script print er, but not to
ot her ty pes of printers .






Eliminated the current mirror (cfr ISSCC 2000) and shrunk
the front end from 260 mm to 125 mm
Put synchronous delay (one column static, other dynamic) in
the empty space and kept other logic identical to 0.5 mm
version
50 mW per pixel
Noise 220-250 e- rms
Threshold dispersion 160 e- rms before 3 bit adjust, 25 e- rms
after
Used three metals only
3500
400
3400
300
electrons
electrons
0.25 mm test chip : 10 keV X-ray Irradiation
Pixel Threshold, Threshold Dispersion and Noise Vs
Total Dose
3300
3200
200
100
0
3100
0.01
0.1
1
10
100
dose (Mrad)
average pixel threshold
0.01
0.1
1
10
100
dose (Mrad)
threshold dispersion (rms)
noise (rms)
Supply currents virtually unaffected during the
irradiation !
2mm
Proton irradiation in NA50
2mm
3.6 x 1013 protons/4mm2
=>
9 x 1014 protons/cm2
Threshold and noise on hit column
after proton irradiation
and 4 hour anneal @ room temperature
(Note: 1 mV = 100 e-)
Proton irradiation in NA50
Conclusions
 Also withstands nonuniform irradiation
 Did not see any evidence
of hard failure, i.e gate
rupture...
Threshold change and noise after proton
irradiation and 20 hour anneal @ room
temperature
Note: 1 mV = 100 e-
Conclusions from test chips
Challenges for full chip



Speed, threshold uniformity and radiation
tolerance (total ionizing dose and single event
upset) proven
Need to further characterize enclosed devices
Challenges for full readout chip :
 Architecture for two different applications
 Large occupancy in LHCb, need to minimize
dead time
 Readout (=digital activity) while being
sensitive
 Large chip
 Large system : testability, uniformity
 Design for radiation tolerance : design
implications revisited
Two applications : pixel for tracking/vertex
finding in ALICE
Half Stave
ladder2
ladder1
10 chips of one half-stave read out sequentially in 400ms
120 half-staves read out in parallel





Minimal mass, thin sensors => 12 000 e- most probable
signal
Spatial resolution of 12mm in r-f => 50 mm pixel pitch
1% average occupancy
Level-1 trigger : latency of 5.5ms, few kHz rate,
buffering on chip
Full event readout in 400ms (deadtime about 10%), 10
And… LHCb RICH : encapsulation of pixel chipsensor assembly in HYBRID PHOTON DETECTOR
for particle ID
 Single photons yield 5000esignal with 20kV accelerating
potential
 2.5mm x 2.5mm channel size, 5
x demagnification =>
500mm  500mm granularity
 8% maximum occupancy
 40 MHz event rate, also
readout clock
 1MHz average Level 0 trigger
rate
 Buffering of Level-0 triggered
events (latency of 4 ms)
 Readout of triggered event in
New 8000 channel chip : pixel
Shaper filterComparator
delay
Preamp
8
BCO
Thres.
3
Cin
analog
test input
test
FF
th
adj
FFs
mask
FF
coinc
logic
strob
e
4-bit
FIFO
RW
data
FF
Two applications : architectural solution
ALICE mode of operation
Title:
Creator:
CorelDRAW
Prev iew :
This EPS picture w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS picture w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.
Two applications : LHCb mode of operation
Title:
Creator:
CorelDRAW
Preview :
This EPS picture w as not saved
w ith a preview included in it.
Comment:
This EPS picture w ill print to a
PostScript printer, but not to
other ty pes of printers .
Voltage [V]
FRONT END
Preamplifier output
0.51
0.5
0.49
0.48
0.47
0.46
0.45
0.44

0.0E+00 5.0E-08
1.0E-07
1.5E-07
2.0E-07
2.5E-07

Shaper Output
0.04
differential voltage [V]
0.02
0
0.0E+00
-0.02
5.0E-08
1.0E-07
1.5E-07
2.0E-07
-0.04
-0.06
-0.08
Vth=20mV
-0.1
-0.12
-0.14
time [s]
2.5E-07
Differential to reject
substrate and supply noise
Closed loop complex poles
for fast return to zero to be
immune to pile-up of
subsequent signals
Pixel Cell : digital part
Delay :
 stores a hit for duration of trigger latency
 latches the time-stamp of a hit from a periodic
Gray-encoded pattern (modulo n) on an 8-bit
bus
FIFO :
 Read/write addressable by Gray encoded bus
Risk of switching noise coupling into analog
circuitry is reduced by:
 Gray encoding of patterns on busses
 Current starved logic cells
Pixel cell
Title:
(pix el_c ell2s.eps )
Creator:
(ImageMagick)
Prev iew :
This EPS picture w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS picture w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.





125mm
pre-amp (differential)
shaper (differential)
discriminator (+ fast-OR)
60mW static consumption







265mm
two digital delay units
trigger coincidence
logic
4-event FIFO buffer
readout logic
35mm
6 metal layers
5 un-upsettable latches for configuration
 test input on/off
1500
transistors/pixel
 pixel mask on/off
layout for
 3 bits of threshold adjust
radiation tolerance
Periphery and I/O




Periphery contains:
 Counters to generate timestamp
 Counters to address FIFO buffers
 8-bit DACs to provide voltage and current
references for analog circuitry and currentstarved logic
I/O pads :Single-ended : Gunning Tranceiver
Logic (GTL)
 Low swing
 Slew rate control
Separate supply for output buffers
Multiple bonding pads for supply lines to reduce
inductance and limit on-chip power supply
Design for testability

Configuration of peripheral logic and pixel cells by
means of JTAG serial interface  allows both write and read of configuration
settings (test,mask….)
 reading back of analog levels (currents &
voltages) generated by DACs
 connectivity tests of chips on stave using
boundary scan allows detection of bad chips on
stave

Every pixel can be addressed individually for testing
using analog input
Very important fine print



Single event effects :
 Single event induced latch-up :
radiation tolerant layout very effective
also here
 Single event upset : special SEU
hardened flip-flops
Power distribution and voltage drops :
 Motivation for (late) decision to switch
from 5 to 6 metal layers
 Local mirroring of sensitive biases to
reduce sensitivity to on-chip resistive
drops
Digital to analog cross-talk :
 Slew rate control on all digital
Conclusions



Experience from omega2 and omega3/LHC1, and from the two
test chips
Commercial deep submicron CMOS allows :
 High component density
 Radiation tolerance
 Good speed-power performance
Full scale pixel readout chip designed
 One chip for Alice pixel vertex and LHCb RICH
 8000 readout channels
 13 M transistors in 14 by 16 mm2
 6 metals
 Testability and system integration
 Uniformity
 Important fine print
Conclusions
Basic building block in full readout
chip :
8 pixels/12 000 transistors in 400 by
2