Transcript ID_311C_Ehrenberg_Goepel_JTAG_BSCAN_V1_1

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ID 311C: Utilizing JTAG / boundary scan and JTAG
emulation for board and system level
test and design verification
GOEPEL Electronics
Heiko Ehrenberg
Managing Director NA Operations
12 October 2010
Version 1.3
Heiko Ehrenberg
 Managing Director of North American Operations at
GOEPEL Electronics LLC
at Austin, TX
 responsible for GOEPEL's operations
in the USA, Canada, and Mexico
 providing support and consulting services
to North American clients
 GOEPEL was founded in 1991 and has ~160 employees
worldwide, active in JTAG/boundary scan, AOI, AXI, and
Functional Test
 Prior Experience:
 Field Application Engineer for JTAG/boundary scan supporting
GOEPEL customers in Germany and then Europe
 BSEE from the University of Applied Sciences at Mittweida,
Germany
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Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
ASIC, ASSP
& Memory
Advanced and
proven technologies
Solutions
for
Innovation
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
*
MCU: 31% revenue basis
from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
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Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
Solutions
for
Innovation
ASIC, ASSP
& Memory
Advanced and
proven technologies
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
*
MCU: 31% revenue basis
from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
4
Microcontroller and Microprocessor Line-up
Superscalar, MMU, Multimedia
High Performance CPU, Low Power
High Performance CPU, FPU, DSC
 Up to 1200 DMIPS, 45, 65 & 90nm process
 Video and audio processing on Linux
 Server, Industrial & Automotive
 Up to 500 DMIPS, 150 & 90nm process
 600uA/MHz, 1.5 uA standby
 Medical, Automotive & Industrial
 Up to 165 DMIPS, 90nm process
 500uA/MHz, 2.5 uA standby
 Ethernet, CAN, USB, Motor Control, TFT Display
 Legacy Cores
 Next-generation migration to RX
General Purpose
 Up to 10 DMIPS, 130nm process
 350 uA/MHz, 1uA standby
 Capacitive touch
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Ultra Low Power
Embedded Security
 Up to 25 DMIPS, 150nm process  Up to 25 DMIPS, 180, 90nm process
 190 uA/MHz, 0.3uA standby
 1mA/MHz, 100uA standby
 Application-specific integration  Crypto engine, Hardware security
Microcontroller and Microprocessor Line-up
Superscalar, MMU, Multimedia
High Performance CPU, Low Power
High Performance CPU, FPU, DSC
 Up to 1200 DMIPS, 45, 65 & 90nm process
 Video and audio processing on Linux
 Server, Industrial & Automotive
 Up to 500 DMIPS, 150 & 90nm process
 600uA/MHz, 1.5 uA standby
 Medical, Automotive & Industrial
 Up to 165 DMIPS, 90nm process
 500uA/MHz, 2.5 uA standby
 Ethernet, CAN, USB, Motor Control, TFT Display
 Legacy Cores
 Next-generation migration to RX
JTAG / boundary scan and
JTAG emulation
for board and system level
General Purpose
Ultra Low Power
test and design
verification
 Up to 10 DMIPS, 130nm process
 350 uA/MHz, 1uA standby
 Capacitive touch
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Embedded Security
 Up to 25 DMIPS, 150nm process  Up to 25 DMIPS, 180, 90nm process
 190 uA/MHz, 0.3uA standby
 1mA/MHz, 100uA standby
 Application-specific integration  Crypto engine, Hardware security
Innovation
Design verification
and prototyping
Manufacturing
test and debug
End of line
(system) test
Field service /
warranty/repair
On-Chip / In-Circuit Emulation
IEEE 1149.x
JTAG / boundary scan
IEEE 1149.x
Functional test
IEEE 1149.x (JTAG / boundary scan) + On-Chip Emulation
Functional test
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Intelligent boundary scan solutions
GOEPEL is a technology leader in JTAG / boundary scan –
creating new, innovative ways to extend the reach of boundary
scan beyond pure structural test applications.
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Agenda
 Benefits and limitations of IEEE Std. 1149.1 for board level
debug and test
 Overview of board and system level JTAG/boundary scan
applications
 Utilization of On-Chip Emulation resources for board level
connectivity test applications
 Interlaced JTAG Emulation and boundary scan testing
 Summary of fault coverage improvements and other benefits
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Key Takeaways
 By the end of this session you will be able to:
 Identify potential board and system level test applications
supported by JTAG/boundary scan on specific board/system
designs;
 Discuss potential test strategies involving JTAG/boundary scan
with test engineering / production test groups
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JTAG / boundary scan in a nutshell
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Boundary scan test applications
R
AND
Gates
Bi-Dir
Buffer
R
SRAM
Digital
Core
Logic
/TRST
TDI
TCK
TMS
/TRST
TDI
TCK
TMS
TDO
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R
ID Reg
R
IR
B
P
TAP
Controller
Digital
Core
Logic
/TRST
TDI
TDO
TCK
TMS
ID Reg
IR
B
P
TAP
Controller
TDO
JTAG / boundary scan limitations ...
 Strictly digital test access (exception: IEEE 1149.4)
 Quasi-static tests (low I/O toggle rate),
limited dynamic test capabilities (exception: BIST)
 Test access determined by BScan capabilities implemented in
devices on the UUT
 BScan test coverage could be improved:
 if test points or connector pins are accessed with Tester I/O
 by accessing analog circuitry with Tester resources
 by utilizing On-Chip Emulation and Tester resources for dynamic,
quasi-functional tests
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Boundary scan
✓
✓
✓
✓
-
vs.
Structural Test
Efficient ATPG tools
Pin Level Diagnostics
In-System Test /
Programming
Flash programming
inefficiencies
Limits in dynamic test
Complexity of cluster
tests
Need for BScan Register
Emulation
✓
✓
✓
✓
-
Functional Test
Fault Coverage
At-Speed Test
FLASH programming speed
µP/µC specific pods
Limited ATPG
Quality of diagnostics
Limited In-System Test /
Programming
How to get the best of both worlds?
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VarioTAP
✓
✓
✓
✓
-
Structural Test
Efficient ATPG tools
Pin Level Diagnostics
In-System Test /
Programming
Flash programming
inefficiencies
Limits in dynamic test
Complexity of cluster
tests
Need for BScan Register
✓
✓
✓
✓
-
Functional Test
Fault Coverage
At-Speed Test
FLASH programming speed
µP/µC specific pods
Limited ATPG
Quality of diagnostics
Limited In-System Test /
Programming
On-Chip Programming + Interlaced Emulation Test
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Classification of boundary scan applications
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Utilization of On-Chip Emulation resources for
board level connectivity test applications
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Emulation Test
Generic μP / MCU / CPU model (On-Chip Resources)
JTAG
PCI Express,
CAN, LIN,
Flexray,
BlueTooth,
WLAN,
USB, LAN,
RS232, ...
Bus IF
Type A
Flash
Analog I/O
Bus IF
Type X
Core
Digital I/O
Internal
Circuits
System
Bus IF
Mixed I/O
Audio,
Video,
Legacy analog,
Legacy digital,
PWM signals,
I2C, SPI,
μW, ...
On-Board Resources: DRAM, External Periphery, Bridges, etc.
Application Type A:
Programming Functions for
On-Chip or external Flash
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Application Type B:
Bus Control Functions for
Bus Emulation Test
Application Type C:
Test Functions for
On-Chip Resources
Flash ISP
TAP
JTAG
JTAG
Bus IF
Type A
PHY
Bus IF
Type X
Core
Digital I/O
Internal
Circuits
System
Bus IF
Mixed I/O
Analog
I/O
JTAG
Flash
Signal Conditioning
PHY
Standard I/O
Standard I/O
Standard I/O
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Bridge
Standard I/FLAS
Standard I/FLASH
Flash
Standard I/RAM
Standard I/RAM
RAM
Standard I/I/O
Standard I/I/O
I/O
Bus Emulation Test
TAP
JTAG
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Bus IF
Type A
PHY
Bus IF
Type X
Core
Digital I/O
Internal
Circuits
System
Bus IF
Mixed I/O
Analog
I/O
JTAG
Flash
Signal Conditioning
PHY
Standard I/O
Standard I/O
Standard I/O
Bridge
Standard I/FLAS
Standard I/FLASH
Flash
Standard I/RAM
Standard I/RAM
RAM
Standard I/I/O
Standard I/I/O
I/O
External Tester
Channels
External Tester
Channels
TAP
JTAG
System Emulation Test
TAP
JTAG
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PHY
Bus IF
Type X
Core
Digital I/O
Internal
Circuits
System
Bus IF
Mixed I/O
Analog
I/O
JTAG
FLASH
External Tester Channels
Bus IF
Type A
Signal Conditioning
PHY
Standard I/O
Standard I/O
Standard I/O
Bridge
Standard I/FLAS
Standard I/FLASH
FLASH
Standard I/RAM
Standard I/RAM
RAM
Standard I/I/O
Standard I/I/O
I/O
External Tester
Channels
External Tester
Channels
TAP
External Tester
Channels
JTAG
VarioTAP application development
Emulation Tool suite for Flash
ISP and Testing
CASLAN Source code
Bscan instruction
VarioTAP Instruction
Bscan Instruction
Compiler
Available
VarioTAP
Commands
Device Model #1
-- Register descriptions
-- Port descriptions
--Device
……. Model #2
-- Register descriptions
-- Port descriptions
Device
-- …….Model #n (µP)
-- Register
descriptions
-- VarioTAP
Model
-- Port descriptions
-- …
-- VarioTAP Model(s)
Selected Device Library
Executable
SYSTEM CASCON™ Environment
 µP/µC specific models are the key for VarioTAP
 Access to VarioTAP functions via CASLAN (high-level
commands)
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VarioTAP applications








Test of Digital I/O
Test of Analog / Mixed-Signal I/O
Fast external Flash Programming
On-Chip Flash Programming
Test of Bus Interfaces
Test of Peripheral Circuitry
Dynamic Memory Access Tests
Customer specific Tests
 Unique: Interlaced utilization of emulation resources and
boundary scan resources
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Fault coverage improvements and other benefits
 Boundary scan provides:
 Embedded test access
 Deterministic test coverage
 Very good diagnostics
 JTAG (on-chip) emulation provides:
 Dynamic fault coverage
 Verification of circuit functions
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Fault coverage improvements and other benefits
 VarioTAP combines boundary scan and on-chip emulation to
provide:
 JTAG controlled functional tests
 Interlaced boundary scan and on-chip emulation tests for
extended connectivity tests
 Automated test generation and deterministic test coverage for
(functional) on-chip emulation tests
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Questions?
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Question 1
 Is there a standard defining JTAG / boundary scan resources?
If so, which standard?
 Yes: IEEE 1149.1
 Also: IEEE 1149.4, IEEE 1149.6, IEEE 1149.7
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Question 2
 Name potential board and system level test applications
supported by JTAG / boundary scan.
 Infrastructure test
 Interconnect test
 Memory access (cluster) test
 Logic cluster test
 In-system programming for Flash, sEEPROM, CPLD
 …
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Question 3
 What is one of the most important printed circuit board level
“design for test” requirements enabling the utilization of
boundary scan capabilities implemented in integrated
circuits?
 Implement a boundary scan chain ! Make the TAP accessible.
 Allow Compliance enable pattern to be satisfied to enable JTAG /
boundary scan compliance.
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Feedback Form
 Please fill out the feedback form!
If you do not have one, please raise your hand
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Thank You!
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Contact information
For further information, please:
Visit our website at www.goepelusa.com
Contact your local sales representative
Call us at 1-888-4GOEPEL
Email us at [email protected]
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Appendix
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References and tools
 White Paper: “Combining Boundary Scan and JTAG Emulation
for advanced structural Test and Diagnostics”
 Boundary Scan Coach:
 software tool demonstrating the key principles of JTAG
/ boundary scan as defined in IEEE 1149.1
 BSDL Syntax Checker:
 software for verification of BSDL syntax and semantics
 TAP Checker:
 software for validation of JTAG / boundary scan
implementations in integrated circuits
 CASCON GALAXY:
 software for device, board, and system level JTAG /
boundary scan test and emulation applications
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