Transcript Lecture 15

CS 3501 - Chapter 3 (3A and 10.2.2)
Part 8 of 8
Dr. Clincy
Professor of CS
Dr. Clincy
Lecture
Slide 1
T Flip Flop
T Flip Flops are good for
counters – changes its
state every clock cycle, if
the input, T, is 1
• Positive-edge triggered flip flop
• Since the previous state of Q was 0,
it complements it to 1
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Lecture
2
Counters
1
T
Clock
Q
T
Q
• 3-stage or 3-bit counter constructed
using T Flip Flops
• With T Flip Flips, when input T=1, the
flip flop toggles – changes state for
each successive clock pulse
• Initially all set to 0
• When clock pulse, Q0=1, therefore
Q’=0 disabling Q1 and Q1 disables Q2
(have 1,0,0)
• For the 2nd clock pulse, Q0=0, therefore
Q’=1, causing Q1=1 and therefore
Q’=0 disabling Q2 (have 0,1,0)
• For the 3rd clock pulse, Q0=1, therefore
Q’=0 disabling Q2 and therefore
disabling Q3 (have 1,1,0)
• Etc….
Q
T
Q
Q0
Q
Q
Q1
Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count
0
1
2
3
4
5
6
7
0
(b) Timing diagram
Figure A.35. A 3-bit up-counter.
LSB
000
001
Hmmm
010
011
100
Dr. Clincy 101
110
111
Lecture
3
Called a Ripple Counter
Circuit
Recall
Combinatorial or Combinational Logic
New Input
Current State or output
of the device is only
affected by the current
inputs
Current
State or
Output
New Input
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Current
State or
Output
Current State or output
of the device is
affected by the
previous states
Flip Flops
Previous
State or
Output
Circuit
Sequential Logic
Examples:
Decoders
Multiplexers
Previous
State or
Output
Lecture
Examples:
Shift Registers
Counters
4
Sequential Circuit – State Diagram
If at 0 and x=0,
count up to 1 (and
z=0)
If x=0, count up,
x=0  z=0
If x=1, count down
S0
If at 0 and x=1,
count down to 3
(and z=0)
S1
Interested when 2
is realized – z=1
when reach 2, else
z=0
x=1  z=0
x = 1  z= 0
x = 0  z= 0
x=0  z=0
x = 1  z= 1
x=1  z=0
S3
S2
x = 0 z = 1
State diagram of a mod-4 up/down counter
that detects the count of 2.
Dr. Clincy
Lecture
State diagram
describes the
functional
behavior without
any reference to
implementation 5
S1
S2
S0
0
0
S2
S3
S1
1
1
S3
S0
S2
0
0
Figure A.48. State table for the example of the up/down counter.
Sequential Circuit – State Table
Can represent the
info in the state
diagram in a state
table
x=0 z=0
S
0
S1
x=1  z=0
x=1 z=0
x=0 z=0
x=0 z=0
x=1 z=1
Present
state
x=1  z=0
S3
x=0 z=1
Next state
Outputz
x =0
x= 1
x=0
x= 1
y2 y1
Y2 Y1
Y2 Y1
0 0
0 1
1 1
0
0
0 1
1 0
0 0
0
0
1 0
1 1
0 1
1
1
1 1
0 0
1 0
0
0
Figure A.49. State assignment for the
xample
e
in Figure A.48.
S
2
State diagram of a mod-4
up/down counter that detects
the count of 2.
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Lecture
6
Sequential Circuit – Equation
Present
state
Next state
Inputs – y2,y1,x
Outputz
x =0
x= 1
x=0
x= 1
y2 y1
Y2 Y1
Y2 Y1
0 0
0 1
1 1
0
0
0 1
1 0
0 0
0
0
1 0
1 1
0 1
1
1
1 1
0 0
1 0
0
0
Figure A.49. State assignment for the
xample
e
in Figure A.48.
Outputs –Y2, Y1
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Lecture
7
Sequential Circuit – Circuit Design
D Flip Flops used
to store values of
the two state
variables between
clock pulses
Output from Flip
Flops is the
present-state of the
variables
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Input, D, of the
Flip Flops is the
next-state of the
variables
Lecture
8
Finite State Machine Model
The example we just implemented is an example of a “Finite State Machine” - is a model
or abstraction of behavior composed of a finite number of states, transitions between
those states, and actions
Input
x
Output
z
y1
Combinational
logic
y2
Y1
Y2
Present
state
Next
state
Delay elements
(f lip-f lops)
Figure A.52. A formal model of a finite state machine.
• Moore finite-state machine – each “state” is associated with an “output”
• Mealy finite-state machine – each “transition” is associated with an “output”
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• Algorithmic
State Machine (ASM) – can actLecture
as both a Moore and Mealy machine
9
NOTE
Your book doesn’t do a good job in showing you how to derive
or design sequential circuits (using state and state assignment
tables) – the lecture did so – your book gives various
examples of sequential circuits (Moore and Mealy finite-state
machines).
Study Guide: For the exams on Monday and Wednesday,
they will cover all of Chapter 3 except the section regarding
transistors (pages 177-178) and Convolutional Coding (pages
178-185). Boolean algebra and circuits can be on both parts
however, the closed book exam will focus more on Boolean
algebra and the opened book exam will focus more on circuits
Dr. Clincy
Lecture
Slide 10
Chapter 3 Review
If any time remains, we can review any topic or
concept for Chapter 3 that was covered in the
lectures. Please keep your questions geared
towards the concepts covered in Ch 3 and the
lectures (in realizing some value-added for the upand-coming exam)
Exam 2 will consists of two parts: Part 1 on Monday and Part 3
on Wednesday. Part 1 will be closed book (can use calculator,
can not use phone or laptop). Part 2 will be open book (can use
calculator and book, can’t use phone or laptop). If you miss
either part of the exam, it can not be made up.
Dr. Clincy
Lecture
Slide 11