Transcript L21a_4345_Sp02

EE 4345 – Semiconductor Electronics
Design Project
Transistor Current Sources and Active Loads
Anuj Shah
Himanshu Doshi
Jayaprakash Chintamaneni
Nareen Katta
Nikhil Patel
Preeti Yadav
Current Sources
Current sources made by using active devices have come to be widely used in
analog integrated circuits as Biasing elements and as load devices for amplifier
stages
The use of current sources in biasing can result in superior insensitivity of circuit
performance to power supply variations and to temperature
A simple 2-transistor current source
Simple current source
Since Q1 and Q2 have the same base-emitter voltage.
Their collector currents are equal, Ic1=Ic2
Summing currents at the collector of Q1 gives,
I ref  I c1  2
I ref
I c1 
 Ic2
2
1
I c1
f
0
I c 2  I ref
Vcc  Vbe (on)

R
f
Thus, For identical devices Q1 and Q2, the output and the reference
Currents are equal
Collector characteristics for an npn transistor
Norton equivalent representation
Of a transistor current source
Thevenin equivalent Representation of a
Transistor current source
Simple current source with current gain
The collector current Ic2 is different form the reference Current by a
factor [ 1 + ( 2/ßf )]
The emitter current of the transistor Q3 is given by,
I c1
f

Ic2
f

2I c 2
f
Summing currents at the collector of Q1,
I ref
2I c 2
 I c1 
0
 f (  f  1)
Since Ic1 and Ic2 are equal,
I ref
Io  Ic2 
2
1 2
f f
Thus, the reference and the output current differ only by a factor
of 1/ßf2
Widlar current source
Widlar current source
Assuming that the transistors are identical and that Vce2 is high enough
to allow Q2 to operate in the active region,The collector current of Q2 is
given by,
 Vbe2 

I c 2  I s exp 
 VT 
Vbe1
 I C1 

 VT ln 
 IS 
Vbe2
 Ic2
 VT ln 
 IS



Voltage equation around the base-emitter loop gives,
Vbe1  Vbe2  R2 I e 2
Solving for R2 gives
I C1
VT
R2 
ln
Ic2
IC 2
Neglecting the base currents,
I c1  I ref
Vcc  Vbe1

R1
Design a widlar current source , given Vcc=15volts. Assume identical
transistors.Also, design a 10uA current mirror and compare total resistance
required in the two circuits.
Let Iref =1mA
15v  0.6v
 14.4k
1mA
 I c1
R2  VT ln 
I
 c2

 1mA 

 10A 
  12k
  0.025 ln 



Design of current mirror,
Vcc  Vbe
R
I ref
15v  0.5v

 1.45M
10A
Cascode current source with bipolar transistors
Performing a full small-signal analysis on this circuit, including the finite
small-signal resistance of Q1 and Q4
We obtain, Ro =ß0 r0/2
Bipolar Wilson current source
Conventional Differential Amplifier
Adm
I c Rc
  g m Rc  
VT

Resistors are used as load elements

Large Voltage Gain – requires large power-supply voltage and
large values of resistors
Example:

and
A voltage gain of 500 would require
I c Rc  13V
I c  100A, Rc would have to be 130K
Current Sources as Active Load
Common-Emitter Amplifier with Active Load
Emitter-Coupled Pair with Active Load
Input Offset Voltage of the Emitter-Coupled Pair with
Active Load
Common-Mode Rejection Ratio of the Emitter-Coupled
Pair with Active Load
Common-Source Amplifier with Active Load
Fig.Common-emitter amplifier with active load
I c1   I c 2
Vce 2  Vcc  Vce1
I c1   I c 2 [( Vcc  Vce1 ), VBE 2 ]
Fig.npn collector characteristic
with pnp Load line superimposed
Initially at Vi=0 at point 1
As Vi Increases at point 2
at point 3
at point 4
Transistors
NPN
PNP
Off
Saturates
On
On
On
On
Saturated
Saturated
Large – Signal Model

V
1  ce1
V AN

I c1

V
 I s1  exp i
VT

Ic2

Vbe 2

  I s 2  exp
VT

I ref

VBE3
  I c3  I s 2  exp
VT

Vce1  V0
Vce 2  Vcc  V0




V
1  ce 2

V AP





 VBE (on) 
1 


VAP 

Fig.dc transfer characteristics Of
common-emitter Amplifier with active
load
V0  [Vcc  VBE ( on) ](
Where, VA( eff )
VAN
)  VA( eff ) [1 
VAN  VAP
I s1 exp
I ref
Vi
VT
]
VANVAP & [V  V
CC
CE ( sat ) ]  V0  [VCE ( sat ) ]
(
)
VAN  VAP
VAN
V0  [VCC  VBE ( on) ](
)
VAN  VAP
Fig.Small-signal equivalent Circuit for
common-emitter Amplifier with active
load
 g m1
 g m1
Av   g m1 (ro1 || ro 2 ) 

1
1
 npn g m1   pnp g m 2

ro1 r02
R0=(ronop+ropon)
Typical values for voltage gain are 1000 to 2000 range.
Fig.Emitter-coupled pair with
Active load
Drawback:
The quiescent value of the common-mode output voltage is very
sensitive to the value of the emitter-biasing current source and
the active-load current sources.
Fig.Common-mode half-circuit for emitter-coupled pair with active load
Output voltage Voc is very sensitive to the voltage at the base of Q6,
which is influence by Iref2.
Example:
If Iref1 and Iref2 are different by 4% , the output voltage Voc will change by
about 2V.
The same change result from a 1mV mismatch between Q6 And Q7.
This circuit eliminates the common-mode problems but provides
a single output with much better rejection of common-mode
Input signals.
Large signal behavior model
Fig.Active-load stage with output connected to a voltage source
Load resistance is zero.
Vbias is adjusted in order to keep Q2 and Q4 in forward Active region.
Ic2
Vbe2
Vce 2
 I s (exp
)(1 
)
VT
VAN
I c 4   I s (exp
Vbe3
Vce 3
I c 3   I s (exp
)(1 
)
VT
VAP
Vbe4
V
)(1  ce 4 )
VT
VAP
Vce1  Vcc  Vbe3  Vbe1  Vcc
Vce 3  VBE ( on)
Vid  Vbe1  Vbe2

 Vid  
 2VA( eff ) tanh 
 
2VT  


Vo  Vcc  VBE (on)  



V

V
V
 1  AN AP tanh  id  
 2V  
 V V
AN
AP
 T 

where
VANVAP
VA (eff ) 
VAN  VAP
 Vid
Vo  Vcc  VBE (on)  2VA( eff ) tanh 
 2VT

Vcc Vo   VBE ( on)  VCE ( sat)




Avd 
VA( eff )
VT
1

VT
 VANVAP 
1

 
 VAN  VAP  VT  VT
VAN VAP
1
Avd 
 g m (ronpnllropnp )
npn   pnp
V
T


EarlyFacto
r

,Where
VA
Early factor is on the order of 2 * 10-4
Device Mismatch Effects:
 Presence of Component mismatches within the Amplifier itself and drifts
of component values with Temperature produce differential voltages at the
output that are indistinguishable from the signal being amplified.
 For Transistor Differential Amplifiers the effect of mismatches is represented
by two Quantities,the input offset voltage and the input offset current.
Circuit Containing Mismatches
Equivalent Circuit with
identically matched devices
Input Offset Voltage is given by the expression
VOS
where
VT 
I c1 I s 2
 VT
I c 2 I s1
kT
 26mV
q
at 300K
Is represents the Saturation Current
2
qni Dn
I sn 
An
N AWBn VCB 
where
Wb(VCB) is the base width of the function VCB
NA is the acceptor density in the base and A is the emitter Area
Input Offset Voltage of the Emitter Coupled Pair with Active
Load
 For a Resistive Load the Input Offset Voltage arises mainly due to the
mismatches in Is in the Input Transistors and from mismatches in the
collector load Resistors.
 For an Active Load the input offset voltage results from mismatches in the
input Transistors and load devices and from the base current of the load
devices.
Emitter Coupled Pair with Active Load
Input Offset Voltage of the Emitter Coupled Pair with Active Load
Vce3  Vce 4
Vce1  Vce 2
and
The Collector Current Ic4 is related to Ic3 by
I 
I c 4  I c 3  s 4 
 I s3 
The Collector Current Q2 is equal to (-Ic4) and thus
 Is4 
I c 2   I c 3  
 I s3 
The Current Ic1 equals (-Ic3),plus the base currents in the pnp transistors
  2
I c1   I c 3 1  
   f




The input offset voltage is given by
 I I   2  
 
Voc  VT ln  s 3 s 2 1  

 I s 4 I s1    f  
In a Worst Case, the Offset Voltage is 0.2VT
These Circuits have significantly higher offset Voltage than the
Resistively loaded case
The offset Voltage can be reduced by inserting resistors in the Emitters of
Q3 and Q4.
Actively Loaded Emitter Coupled Pair for improved Offset
Common-Mode Rejection Ratio of the Emitter Coupled Pair with
Active Load
 CMRR is defined as the Magnitude of the ratio of differential to
Common Mode Gain.
 Provides conversion from a differential signal to a signal that is
referenced to ground.This type of Conversion is required in all
differential input,single-ended output amplifiers.
Simplest differential to single-ended converter is the resistively
Loaded emitter coupled pair.
Differential to Single ended Conversion
Using resistively loaded Emitter coupled Pair
Differential to Single ended Conversion
Using actively loaded Emitter coupled Pair
The output is given by Vo  
Adm 
2Vic 
Vid 

2 
CMRR 

1 
CMRR  1  2 g m REE 1  
  
Transistor Q3 operates at twice the current of Q1 and Q2
CMRR  g m 3 ro 3 
1
3
CMRR of the resistively loaded stage is the inverse of the  of the current
source Transistor when a simple current source is used as a biasing element.
For an active-loaded case
In case of Resistively loaded case ,changes in the common Mode input will cause
changes in the bias current IEE because of the finite output resistance of the biasing
current source.This will cause a change in Ic2 and an identical change in Ic1.
Because of the active load ,the change in Ic1 will produce a change in the currents
flowing in the pnp load transistors ,which produces a change in the collecter current
of Q2.So the output does not change at all in response to common Mode Inputs.
Analytically
CMRR 
Adm  Vos 

 
Acm  Vic 
1
Common-Source Amplifier with Active Load
Common Source Amplifier using an NMOS driver and PMOS active
load.
When M1 and M2 are forward active,the small signal gain is
g m1
Av  
g o1  g o 2
Gain for NMOS depletion-load transistor
g m1
Av  
g mb 2
Common-Source Amplifier with p channel transistor
Current source load
Transfer Characteristic
I-V Characteristic of n-channel depletion mode load transistor
Common Source Amplifier with depletion mode transistor load
and dc transfer characteristic
Common Source Amplifier with Enhancement-Mode load
Common-Source Amplifier with enhancement-mode load and transfer characteristic
Av  
W / L1
g m1

W / L 2
gm2
Source Coupled Pair with Active load
Av  
g m1
go2  go4
 Widely used in CMOS Circuit Design
References:
 Analysis and Design of Analog Integrated Circuits, 3rd Edition
by Paul R.Gray and Robert G.Meyer.
Analog integrated circuit design,1st edition by David Johns and Ken
Martin
 Electronics,2nd Edition, by Allan R.Hambley