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SET Fault Tolerant Combinational Circuits Based on Majority Logic
Álisson Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Kastensmidt and Luigi Carro
DFT 2006
INFORMÁTICA
 One voter (as used in TMR) implements the majority function
 Majority gates (MGs) can be used to implement AND and OR functions
 An analog comparator can be used to implement fault tolerant MGs
 This comparator can also be used to implement a fault tolerant inverter
Due to that, MGs can be used to implement
AOI combinational logic that is tolerant to
multiple simultaneous transient errors
Single Event Upset Origin
Motivation
10100001
• in future technologies, propagation delays will be shorter than the duration of transient pulses
• smaller transistors will be more sensitive to electromagnetic noise and neutron and alpha particles
• industry experts believe that the possibility of simultaneous faults is no longer neglectable
• the classic Triple Modular Redundancy approach can not withstand more than one fault at a time
TMR weaknesses
01011110
11011110
The analog voter: a fault tolerant solution
 TMR does not protect against two simultaneous faults affecting
different modules
 brings knowledge from the analog arena
 faults injected in several nodes
 When a single fault occurs in the voter circuit, the voter output
may be wrong
Module 1
Module 1
wrong output
Module 2
correct output
Module 3
wrong output
V
O
T
E
R
wrong output
a
b
1
Injection of faults
in the comparator
correct output
Module 2
correct output
Module 3
correct output
Using majority logic to implement AOI circuits
a
b
0
 no effect on output of the voter
V
O
T
E
R
correct output ?
Sample circuit implementation: full adder
Input
-
MG3
MG3
+
maj(a, b, 0) = a.b + a.0 + b.0 = a.b
(AND gate)
maj(a, b, 1) = a.b + a.1 + b.1 = a.b + a + b = a + b
(OR gate)
Output
Classic TMR implementation:
Vref = Vdd/2
- 3 standard AOI full adder modules
Analog inverter
- 1 digital voter per output bit
(INVERTER)
Note: majority gates and inverters implemented with the analog comparator are also fault tolerant
Proposed solution:
Achieved metrics (area  delay  power tradeoffs yet to be explored):
 single full adder module
 36% less area than the TMR technique
 majority gates implementing AND/OR functions
 44% less delay than the TMR technique
 analog comparators implementing majority gates and
 71% higher power consumption than the TMR technique
inverters
Area
comparison
Area
comparison
Delay Delay
andand
Power
Consum ption
power consumption
1
0,9
0,8
0,7
0,6
TMR
TMR
TMR
TMR
0,5
Analog
MGs
Analog
Analog
MGsMGs
Analog
MGs
0,4
0,3
0,2
0,1
0
Delay
Delay
Area (nm²)
Area
(nm²)
Circuit
Area
(nm2)
Relative
Area
Power
Power
Classic TMR 8,744,960
1.00
Delay Relative Power Relative
(ps)
Delay (W) Power
Classic TMR 81
1.00
210
1.00
Analog MGs 5,581,310
0.64
Analog MGs
Circuit
45
0.56
360
1.71
Porto Alegre - RS
BRAZIL
Universidade Federal do Rio Grande do Sul - UFRGS
Instituto de Informática, Pós-Graduação em Ciência da Computação
Grupo de Microeletrônica (GME) - Laboratório de Sistemas Embarcados (LSE)
http://www.inf.ufrgs.br/gme, http://www.inf.ufrgs.br/~lse
Phone
+55 51 3316.6165
e-mail
lpetroli@inf,ufrgs.br
[email protected]
[email protected]
[email protected]
[email protected]